1 /* $NetBSD: pciconf.c,v 1.64 2026/08/20 06:51:57 msaitoh Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.64 2026/08/20 06:51:57 msaitoh Exp $"); 69 70 #include "opt_pci.h" 71 72 #include <sys/param.h> 73 #include <sys/queue.h> 74 #include <sys/systm.h> 75 #include <sys/kmem.h> 76 #include <sys/vmem.h> 77 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pciconf.h> 80 #include <dev/pci/pcidevs.h> 81 #include <dev/pci/pccbbreg.h> 82 83 int pci_conf_debug = 0; 84 85 #if !defined(MIN) 86 #define MIN(a,b) (((a)<(b))?(a):(b)) 87 #define MAX(a,b) (((a)>(b))?(a):(b)) 88 #endif 89 90 /* per-bus constants. */ 91 #define MAX_CONF_DEV 32 /* Arbitrary */ 92 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 93 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 94 95 #define PCICONF_MAPREG_IS_ROM(reg) \ 96 (((reg) == PCI_MAPREG_ROM) || ((reg) == PCI_BRIDGE_EXPROMADDR_REG)) 97 98 struct _s_pciconf_bus_t; /* Forward declaration */ 99 100 struct pciconf_resource { 101 vmem_t *arena; 102 bus_addr_t min_addr; 103 bus_addr_t max_addr; 104 bus_size_t total_size; 105 }; 106 107 #define PCICONF_RESOURCE_NTYPES 3 108 CTASSERT(PCICONF_RESOURCE_IO < PCICONF_RESOURCE_NTYPES); 109 CTASSERT(PCICONF_RESOURCE_MEM < PCICONF_RESOURCE_NTYPES); 110 CTASSERT(PCICONF_RESOURCE_PREFETCHABLE_MEM < PCICONF_RESOURCE_NTYPES); 111 112 static const char *pciconf_resource_names[] = { 113 [PCICONF_RESOURCE_IO] = "pci-io", 114 [PCICONF_RESOURCE_MEM] = "pci-mem", 115 [PCICONF_RESOURCE_PREFETCHABLE_MEM] = "pci-pmem", 116 }; 117 118 struct pciconf_resources { 119 struct pciconf_resource resources[PCICONF_RESOURCE_NTYPES]; 120 }; 121 122 struct pciconf_resource_rsvd { 123 int type; 124 uint64_t start; 125 bus_size_t size; 126 void (*callback)(void *, uint64_t); 127 void *callback_arg; 128 LIST_ENTRY(pciconf_resource_rsvd) next; 129 }; 130 131 static LIST_HEAD(, pciconf_resource_rsvd) pciconf_resource_reservations = 132 LIST_HEAD_INITIALIZER(pciconf_resource_reservations); 133 134 typedef struct _s_pciconf_dev_t { 135 int ipin; 136 int iline; 137 int min_gnt; 138 int max_lat; 139 int enable; 140 pcitag_t tag; 141 pci_chipset_tag_t pc; 142 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 143 pcireg_t ea_cap_ptr; 144 } pciconf_dev_t; 145 146 typedef struct _s_pciconf_win_t { 147 pciconf_dev_t *dev; 148 int reg; /* 0 for busses */ 149 int prefetch; 150 uint64_t size; 151 uint64_t address; 152 uint64_t align; 153 } pciconf_win_t; 154 155 typedef struct _s_pciconf_bus_t { 156 int busno; 157 int next_busno; 158 int last_busno; 159 int max_mingnt; 160 int min_maxlat; 161 int cacheline_size; 162 int prefetch; 163 int fast_b2b; 164 int freq_66; 165 int def_ltim; 166 int max_ltim; 167 int bandwidth_used; 168 int swiz; 169 int io_32bit; 170 int pmem_64bit; 171 int mem_64bit; 172 173 int ndevs; 174 pciconf_dev_t device[MAX_CONF_DEV]; 175 176 /* These should be sorted in order of decreasing alignment */ 177 int nmemwin; 178 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 179 int niowin; 180 pciconf_win_t pciiowin[MAX_CONF_IO]; 181 182 bus_size_t io_total; 183 bus_size_t mem_total; 184 bus_size_t pmem_total; 185 bus_size_t io_align; 186 bus_size_t mem_align; 187 bus_size_t pmem_align; 188 189 struct pciconf_resource io_res; 190 struct pciconf_resource mem_res; 191 struct pciconf_resource pmem_res; 192 193 pci_chipset_tag_t pc; 194 struct _s_pciconf_bus_t *parent_bus; 195 } pciconf_bus_t; 196 197 static int probe_bus(pciconf_bus_t *); 198 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 199 static void set_busreg(pci_chipset_tag_t, pcitag_t, int, int, int); 200 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 201 static int setup_iowins(pciconf_bus_t *); 202 static int setup_memwins(pciconf_bus_t *); 203 static int configure_bridge(pciconf_dev_t *); 204 static int configure_bus(pciconf_bus_t *); 205 static uint64_t pci_allocate_range(struct pciconf_resource *, uint64_t, int, 206 bool); 207 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 208 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 209 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 210 211 static void print_tag(pci_chipset_tag_t, pcitag_t); 212 213 static vmem_t * 214 create_vmem_arena(const char *name, bus_addr_t start, bus_size_t size, 215 int flags) 216 { 217 KASSERT(start < VMEM_ADDR_MAX); 218 KASSERT(size == 0 || 219 (VMEM_ADDR_MAX - start) >= (size - 1)); 220 221 return vmem_create(name, start, size, 222 1, /*quantum*/ 223 NULL, /*importfn*/ 224 NULL, /*releasefn*/ 225 NULL, /*source*/ 226 0, /*qcache_max*/ 227 flags, 228 IPL_NONE); 229 } 230 231 static int 232 init_range_resource(struct pciconf_resource *r, const char *name, 233 bus_addr_t start, bus_addr_t size) 234 { 235 r->arena = create_vmem_arena(name, start, size, VM_NOSLEEP); 236 if (r->arena == NULL) 237 return ENOMEM; 238 239 r->min_addr = start; 240 r->max_addr = start + (size - 1); 241 r->total_size = size; 242 243 return 0; 244 } 245 246 static void 247 fini_range_resource(struct pciconf_resource *r) 248 { 249 if (r->arena) { 250 vmem_xfreeall(r->arena); 251 vmem_destroy(r->arena); 252 } 253 memset(r, 0, sizeof(*r)); 254 } 255 256 static void 257 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 258 { 259 int bus, dev, func; 260 261 pci_decompose_tag(pc, tag, &bus, &dev, &func); 262 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 263 } 264 265 #ifdef _LP64 266 #define __used_only_lp64 __unused 267 #else 268 #define __used_only_lp64 /* nothing */ 269 #endif /* _LP64 */ 270 271 /************************************************************************/ 272 /************************************************************************/ 273 /*********************** Bus probing routines ***********************/ 274 /************************************************************************/ 275 /************************************************************************/ 276 static pciconf_win_t * 277 get_io_desc(pciconf_bus_t *pb, bus_size_t align) 278 { 279 int i, n; 280 281 n = pb->niowin; 282 for (i = n; i > 0 && align > pb->pciiowin[i-1].align; i--) 283 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 284 return &pb->pciiowin[i]; 285 } 286 287 static pciconf_win_t * 288 get_mem_desc(pciconf_bus_t *pb, bus_size_t align) 289 { 290 int i, n; 291 292 n = pb->nmemwin; 293 for (i = n; i > 0 && align > pb->pcimemwin[i-1].align; i--) 294 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 295 return &pb->pcimemwin[i]; 296 } 297 298 /* 299 * Set up bus common stuff, then loop over devices & functions. 300 * If we find something, call pci_do_device_query()). 301 */ 302 static int 303 probe_bus(pciconf_bus_t *pb) 304 { 305 int device; 306 uint8_t devs[32]; 307 int i, n; 308 309 pb->ndevs = 0; 310 pb->niowin = 0; 311 pb->nmemwin = 0; 312 pb->freq_66 = 1; 313 #ifdef PCICONF_NO_FAST_B2B 314 pb->fast_b2b = 0; 315 #else 316 pb->fast_b2b = 1; 317 #endif 318 pb->prefetch = 1; 319 pb->max_mingnt = 0; /* we are looking for the maximum */ 320 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 321 pb->bandwidth_used = 0; 322 323 n = pci_bus_devorder(pb->pc, pb->busno, devs, __arraycount(devs)); 324 for (i = 0; i < n; i++) { 325 pcitag_t tag; 326 pcireg_t id, bhlcr; 327 int function, nfunction; 328 int confmode; 329 330 device = devs[i]; 331 332 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 333 if (pci_conf_debug) { 334 print_tag(pb->pc, tag); 335 } 336 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 337 338 if (pci_conf_debug) { 339 printf("id=%x: Vendor=%x, Product=%x\n", 340 id, PCI_VENDOR(id), PCI_PRODUCT(id)); 341 } 342 /* Invalid vendor ID value? */ 343 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 344 continue; 345 346 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 347 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 348 for (function = 0; function < nfunction; function++) { 349 tag = pci_make_tag(pb->pc, pb->busno, device, function); 350 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 351 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 352 continue; 353 if (pb->ndevs + 1 < MAX_CONF_DEV) { 354 if (pci_conf_debug) { 355 print_tag(pb->pc, tag); 356 printf("Found dev 0x%04x 0x%04x -- " 357 "really probing.\n", 358 PCI_VENDOR(id), PCI_PRODUCT(id)); 359 } 360 #ifdef __HAVE_PCI_CONF_HOOK 361 confmode = pci_conf_hook(pb->pc, pb->busno, 362 device, function, id); 363 if (confmode == 0) 364 continue; 365 #else 366 /* 367 * Don't enable expansion ROMS -- some cards 368 * share address decoders between the EXPROM 369 * and PCI memory space, and enabling the ROM 370 * when not needed will cause all sorts of 371 * lossage. 372 */ 373 confmode = PCI_CONF_DEFAULT; 374 #endif 375 if (pci_do_device_query(pb, tag, device, 376 function, confmode)) 377 return -1; 378 pb->ndevs++; 379 } 380 } 381 } 382 return 0; 383 } 384 385 static void 386 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 387 { 388 pb->busno = parent->next_busno; 389 pb->next_busno = pb->busno + 1; 390 } 391 392 static void 393 set_busreg(pci_chipset_tag_t pc, pcitag_t tag, int prim, int sec, int sub) 394 { 395 pcireg_t busreg; 396 397 busreg = __SHIFTIN(prim, PCI_BRIDGE_BUS_PRIMARY); 398 busreg |= __SHIFTIN(sec, PCI_BRIDGE_BUS_SECONDARY); 399 busreg |= __SHIFTIN(sub, PCI_BRIDGE_BUS_SUBORDINATE); 400 pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg); 401 } 402 403 static pciconf_bus_t * 404 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 405 { 406 pciconf_bus_t *pb; 407 pcireg_t io, pmem; 408 pciconf_win_t *pi, *pm; 409 410 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_SLEEP); 411 pb->cacheline_size = parent->cacheline_size; 412 pb->parent_bus = parent; 413 alloc_busno(parent, pb); 414 415 pb->mem_align = 0x100000; /* 1M alignment */ 416 pb->pmem_align = 0x100000; /* 1M alignment */ 417 pb->io_align = 0x1000; /* 4K alignment */ 418 419 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff); 420 421 pb->swiz = parent->swiz + dev; 422 423 memset(&pb->io_res, 0, sizeof(pb->io_res)); 424 memset(&pb->mem_res, 0, sizeof(pb->mem_res)); 425 memset(&pb->pmem_res, 0, sizeof(pb->pmem_res)); 426 427 pb->pc = parent->pc; 428 pb->io_total = pb->mem_total = pb->pmem_total = 0; 429 430 pb->io_32bit = 0; 431 if (parent->io_32bit) { 432 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 433 if (PCI_BRIDGE_IO_32BITS(io)) 434 pb->io_32bit = 1; 435 } 436 437 pb->pmem_64bit = 0; 438 if (parent->pmem_64bit) { 439 pmem = pci_conf_read(parent->pc, pd->tag, 440 PCI_BRIDGE_PREFETCHMEM_REG); 441 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) 442 pb->pmem_64bit = 1; 443 } 444 445 /* Bridges only forward a 32-bit range of non-prefetcable memory. */ 446 pb->mem_64bit = 0; 447 448 if (probe_bus(pb)) { 449 printf("Failed to probe bus %d\n", pb->busno); 450 goto err; 451 } 452 453 /* We have found all subordinate busses now, reprogram busreg. */ 454 pb->last_busno = pb->next_busno - 1; 455 parent->next_busno = pb->next_busno; 456 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 457 pb->last_busno); 458 if (pci_conf_debug) 459 printf("PCI bus bridge (parent %d) covers busses %d-%d\n", 460 parent->busno, pb->busno, pb->last_busno); 461 462 if (pb->io_total > 0) { 463 if (parent->niowin >= MAX_CONF_IO) { 464 printf("pciconf: too many (%d) I/O windows\n", 465 parent->niowin); 466 goto err; 467 } 468 pb->io_total = roundup2(pb->io_total, pb->io_align); 469 pi = get_io_desc(parent, pb->io_align); 470 pi->dev = pd; 471 pi->reg = 0; 472 pi->size = pb->io_total; 473 pi->align = pb->io_align; /* 4K min alignment */ 474 if (parent->io_align < pb->io_align) 475 parent->io_align = pb->io_align; 476 pi->prefetch = 0; 477 parent->niowin++; 478 parent->io_total += pb->io_total; 479 } 480 481 if (pb->mem_total > 0) { 482 if (parent->nmemwin >= MAX_CONF_MEM) { 483 printf("pciconf: too many (%d) MEM windows\n", 484 parent->nmemwin); 485 goto err; 486 } 487 pb->mem_total = roundup2(pb->mem_total, pb->mem_align); 488 pm = get_mem_desc(parent, pb->mem_align); 489 pm->dev = pd; 490 pm->reg = 0; 491 pm->size = pb->mem_total; 492 pm->align = pb->mem_align; /* 1M min alignment */ 493 if (parent->mem_align < pb->mem_align) 494 parent->mem_align = pb->mem_align; 495 pm->prefetch = 0; 496 parent->nmemwin++; 497 parent->mem_total += pb->mem_total; 498 } 499 500 if (pb->pmem_total > 0) { 501 if (parent->nmemwin >= MAX_CONF_MEM) { 502 printf("pciconf: too many MEM windows\n"); 503 goto err; 504 } 505 pb->pmem_total = roundup2(pb->pmem_total, pb->pmem_align); 506 pm = get_mem_desc(parent, pb->pmem_align); 507 pm->dev = pd; 508 pm->reg = 0; 509 pm->size = pb->pmem_total; 510 pm->align = pb->pmem_align; /* 1M min alignment */ 511 if (parent->pmem_align < pb->pmem_align) 512 parent->pmem_align = pb->pmem_align; 513 pm->prefetch = 1; 514 parent->nmemwin++; 515 parent->pmem_total += pb->pmem_total; 516 } 517 518 return pb; 519 err: 520 kmem_free(pb, sizeof(*pb)); 521 return NULL; 522 } 523 524 static struct pciconf_resource_rsvd * 525 pci_resource_is_reserved(int type, uint64_t addr, uint64_t size) 526 { 527 struct pciconf_resource_rsvd *rsvd; 528 529 LIST_FOREACH(rsvd, &pciconf_resource_reservations, next) { 530 if (rsvd->type != type) 531 continue; 532 if (rsvd->start <= addr + size && 533 rsvd->start + rsvd->size >= addr) 534 return rsvd; 535 } 536 537 return NULL; 538 } 539 540 static struct pciconf_resource_rsvd * 541 pci_bar_is_reserved(pciconf_bus_t *pb, pciconf_dev_t *pd, int br) 542 { 543 pcireg_t base, base64, mask, mask64; 544 pcitag_t tag; 545 uint64_t addr, size; 546 547 /* 548 * Resource reservation does not apply to bridges 549 */ 550 if (pd->ppb) 551 return NULL; 552 553 tag = pd->tag; 554 555 /* 556 * Look to see if this device is enabled and one of the resources 557 * is already in use (eg. firmware configured console device). 558 */ 559 base = pci_conf_read(pb->pc, tag, br); 560 pci_conf_write(pb->pc, tag, br, 0xffffffff); 561 mask = pci_conf_read(pb->pc, tag, br); 562 pci_conf_write(pb->pc, tag, br, base); 563 564 switch (PCI_MAPREG_TYPE(base)) { 565 case PCI_MAPREG_TYPE_IO: 566 addr = PCI_MAPREG_IO_ADDR(base); 567 size = PCI_MAPREG_IO_SIZE(mask); 568 return pci_resource_is_reserved(PCI_CONF_MAP_IO, addr, size); 569 570 case PCI_MAPREG_TYPE_MEM: 571 if (PCI_MAPREG_MEM_TYPE(base) == PCI_MAPREG_MEM_TYPE_64BIT) { 572 base64 = pci_conf_read(pb->pc, tag, br + 4); 573 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 574 mask64 = pci_conf_read(pb->pc, tag, br + 4); 575 pci_conf_write(pb->pc, tag, br + 4, base64); 576 addr = (uint64_t)PCI_MAPREG_MEM64_ADDR( 577 (((uint64_t)base64) << 32) | base); 578 size = (uint64_t)PCI_MAPREG_MEM64_SIZE( 579 (((uint64_t)mask64) << 32) | mask); 580 } else { 581 addr = PCI_MAPREG_MEM_ADDR(base); 582 size = PCI_MAPREG_MEM_SIZE(mask); 583 } 584 return pci_resource_is_reserved(PCI_CONF_MAP_MEM, addr, size); 585 586 default: 587 return NULL; 588 } 589 } 590 591 static int 592 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, 593 int mode) 594 { 595 pciconf_dev_t *pd; 596 pciconf_win_t *pi, *pm; 597 pcireg_t classreg, cmd, icr, bhlc, bar, mask, bar64, mask64, 598 busreg; 599 uint64_t size; 600 u_int hdrtype, br, width, reg_start, reg_end, reg_rom; 601 602 pd = &pb->device[pb->ndevs]; 603 pd->pc = pb->pc; 604 pd->tag = tag; 605 pd->ppb = NULL; 606 pd->enable = mode; 607 pd->ea_cap_ptr = 0; 608 609 classreg = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 610 611 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 612 bhlc = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 613 614 if (pci_get_capability(pb->pc, tag, PCI_CAP_EA, &pd->ea_cap_ptr, 615 NULL)) { 616 /* XXX Skip devices with EA for now. */ 617 print_tag(pb->pc, tag); 618 printf("skipping devices with Enhanced Allocations\n"); 619 return 0; 620 } 621 622 hdrtype = PCI_HDRTYPE_TYPE(bhlc); 623 if (PCI_CLASS(classreg) != PCI_CLASS_BRIDGE 624 && hdrtype != PCI_HDRTYPE_PPB) { 625 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 626 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 627 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 628 } else if (pci_conf_debug) { 629 print_tag(pb->pc, tag); 630 printf("device is a bridge; not clearing enables\n"); 631 } 632 633 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 634 pb->fast_b2b = 0; 635 636 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 637 pb->freq_66 = 0; 638 639 reg_rom = PCI_MAPREG_ROM; /* Default */ 640 switch (hdrtype) { 641 case PCI_HDRTYPE_DEVICE: 642 reg_start = PCI_MAPREG_START; 643 reg_end = PCI_MAPREG_END; 644 break; 645 case PCI_HDRTYPE_PPB: 646 pd->ppb = query_bus(pb, pd, dev); 647 if (pd->ppb == NULL) 648 return -1; 649 /* 650 * PCI-to-PCI Bridge Spec rev. 1.2. 651 * "3.2.5.1 Base Address registers" says that if the optional 652 * BARs are implemented, the configuration software must map 653 * address ranges. 654 */ 655 reg_start = PCI_MAPREG_START; 656 reg_end = PCI_MAPREG_PPB_END; /* Only BAR0 and BAR1 */ 657 reg_rom = PCI_BRIDGE_EXPROMADDR_REG; 658 break; 659 case PCI_HDRTYPE_PCB: 660 reg_start = PCI_MAPREG_START; 661 reg_end = PCI_MAPREG_PCB_END; 662 663 busreg = pci_conf_read(pb->pc, tag, PCI_BUSNUM); 664 busreg = (busreg & 0xff000000) | 665 __SHIFTIN(pb->busno, PCI_BRIDGE_BUS_PRIMARY) | 666 __SHIFTIN(pb->next_busno, PCI_BRIDGE_BUS_SECONDARY) | 667 __SHIFTIN(pb->next_busno, PCI_BRIDGE_BUS_SUBORDINATE); 668 pci_conf_write(pb->pc, tag, PCI_BUSNUM, busreg); 669 670 pb->next_busno++; 671 break; 672 default: 673 return -1; 674 } 675 676 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 677 pd->ipin = PCI_INTERRUPT_PIN(icr); 678 pd->iline = PCI_INTERRUPT_LINE(icr); 679 if (pd->iline || pd->ipin) { 680 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 681 &pd->iline); 682 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 683 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 684 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 685 } 686 687 /* For non-PPB devices */ 688 if (hdrtype != PCI_HDRTYPE_PPB) { 689 pd->min_gnt = PCI_MIN_GNT(icr); 690 pd->max_lat = PCI_MAX_LAT(icr); 691 if (pd->min_gnt != 0 || pd->max_lat != 0) { 692 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 693 pb->max_mingnt = pd->min_gnt; 694 695 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 696 pb->min_maxlat = pd->max_lat; 697 698 pb->bandwidth_used += pd->min_gnt * 4000000 / 699 (pd->min_gnt + pd->max_lat); 700 } 701 } 702 703 width = 4; 704 for (br = reg_start; br < reg_end; br += width) { 705 #if 0 706 /* XXX Should only ignore if IDE not in legacy mode? */ 707 if (PCI_CLASS(classreg) == PCI_CLASS_MASS_STORAGE && 708 PCI_SUBCLASS(classreg) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 709 break; 710 } 711 #endif 712 bar = pci_conf_read(pb->pc, tag, br); 713 pci_conf_write(pb->pc, tag, br, 0xffffffff); 714 mask = pci_conf_read(pb->pc, tag, br); 715 pci_conf_write(pb->pc, tag, br, bar); 716 width = 4; 717 718 if ( (mode & PCI_CONF_MAP_IO) 719 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 720 /* 721 * Upper 16 bits must be one. Devices may hardwire 722 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 723 */ 724 mask |= 0xffff0000; 725 726 size = PCI_MAPREG_IO_SIZE(mask); 727 if (size == 0) { 728 if (pci_conf_debug) { 729 print_tag(pb->pc, tag); 730 printf("I/O BAR 0x%x is void\n", br); 731 } 732 continue; 733 } 734 735 if (pb->niowin >= MAX_CONF_IO) { 736 printf("pciconf: too many I/O windows\n"); 737 return -1; 738 } 739 740 pi = get_io_desc(pb, size /*align*/); 741 pi->dev = pd; 742 pi->reg = br; 743 pi->size = pi->align = size; 744 if (pb->io_align < pi->align) 745 pb->io_align = pi->align; 746 pi->prefetch = 0; 747 if (pci_conf_debug) { 748 print_tag(pb->pc, tag); 749 printf("Register 0x%x, I/O size %" PRIu64 "\n", 750 br, pi->size); 751 } 752 pb->niowin++; 753 pb->io_total += size; 754 } else if ((mode & PCI_CONF_MAP_MEM) 755 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 756 switch (PCI_MAPREG_MEM_TYPE(mask)) { 757 case PCI_MAPREG_MEM_TYPE_32BIT: 758 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 759 size = (uint64_t)PCI_MAPREG_MEM_SIZE(mask); 760 break; 761 case PCI_MAPREG_MEM_TYPE_64BIT: 762 bar64 = pci_conf_read(pb->pc, tag, br + 4); 763 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 764 mask64 = pci_conf_read(pb->pc, tag, br + 4); 765 pci_conf_write(pb->pc, tag, br + 4, bar64); 766 size = (uint64_t)PCI_MAPREG_MEM64_SIZE( 767 (((uint64_t)mask64) << 32) | mask); 768 width = 8; 769 break; 770 default: 771 print_tag(pb->pc, tag); 772 printf("reserved mapping type 0x%x\n", 773 PCI_MAPREG_MEM_TYPE(mask)); 774 continue; 775 } 776 777 if (size == 0) { 778 if (pci_conf_debug) { 779 print_tag(pb->pc, tag); 780 printf("MEM%d BAR 0x%x is void\n", 781 PCI_MAPREG_MEM_TYPE(mask) == 782 PCI_MAPREG_MEM_TYPE_64BIT ? 783 64 : 32, br); 784 } 785 continue; 786 } else { 787 if (pci_conf_debug) { 788 print_tag(pb->pc, tag); 789 printf("MEM%d BAR 0x%x has size %#lx\n", 790 PCI_MAPREG_MEM_TYPE(mask) == 791 PCI_MAPREG_MEM_TYPE_64BIT ? 792 64 : 32, 793 br, (unsigned long)size); 794 } 795 } 796 797 if (pb->nmemwin >= MAX_CONF_MEM) { 798 printf("pciconf: too many memory windows\n"); 799 return -1; 800 } 801 802 pm = get_mem_desc(pb, size /*align*/); 803 pm->dev = pd; 804 pm->reg = br; 805 pm->size = pm->align = size; 806 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 807 if (pci_conf_debug) { 808 print_tag(pb->pc, tag); 809 printf("Register 0x%x, memory size %" 810 PRIu64 "\n", br, pm->size); 811 } 812 pb->nmemwin++; 813 if (pm->prefetch) { 814 pb->pmem_total += size; 815 if (pb->pmem_align < pm->align) 816 pb->pmem_align = pm->align; 817 } else { 818 pb->mem_total += size; 819 if (pb->mem_align < pm->align) 820 pb->mem_align = pm->align; 821 } 822 } 823 } 824 825 if (mode & PCI_CONF_MAP_ROM) { 826 bar = pci_conf_read(pb->pc, tag, reg_rom); 827 pci_conf_write(pb->pc, tag, reg_rom, 0xfffffffe); 828 mask = pci_conf_read(pb->pc, tag, reg_rom); 829 pci_conf_write(pb->pc, tag, reg_rom, bar); 830 831 if (mask != 0 && mask != 0xffffffff) { 832 if (pb->nmemwin >= MAX_CONF_MEM) { 833 printf("pciconf: too many memory windows\n"); 834 return -1; 835 } 836 size = (uint64_t)PCI_MAPREG_MEM_SIZE(mask); 837 838 pm = get_mem_desc(pb, size /*align*/); 839 pm->dev = pd; 840 pm->reg = reg_rom; 841 pm->size = pm->align = size; 842 pm->prefetch = 0; 843 if (pci_conf_debug) { 844 print_tag(pb->pc, tag); 845 printf("Expansion ROM memory size %" 846 PRIu64 "\n", pm->size); 847 } 848 pb->nmemwin++; 849 if (pm->prefetch) { 850 pb->pmem_total += size; 851 if (pb->pmem_align < pm->align) 852 pb->pmem_align = pm->align; 853 } else { 854 pb->mem_total += size; 855 if (pb->mem_align < pm->align) 856 pb->mem_align = pm->align; 857 } 858 } 859 } else { 860 /* Don't enable ROMs if we aren't going to map them. */ 861 mode &= ~PCI_CONF_ENABLE_ROM; 862 pd->enable &= ~PCI_CONF_ENABLE_ROM; 863 } 864 865 if (!(mode & PCI_CONF_ENABLE_ROM)) { 866 /* Ensure ROM is disabled */ 867 bar = pci_conf_read(pb->pc, tag, reg_rom); 868 pci_conf_write(pb->pc, tag, reg_rom, 869 bar & ~PCI_MAPREG_ROM_ENABLE); 870 } 871 872 return 0; 873 } 874 875 /************************************************************************/ 876 /************************************************************************/ 877 /******************** Bus configuration routines ********************/ 878 /************************************************************************/ 879 /************************************************************************/ 880 static uint64_t 881 pci_allocate_range(struct pciconf_resource * const r, const uint64_t amt, 882 const int align, const bool ok64 __used_only_lp64) 883 { 884 vmem_size_t const size = (vmem_size_t) amt; 885 vmem_addr_t result; 886 int error; 887 888 #ifdef _LP64 889 /* 890 * If a 64-bit range IS OK, then we prefer allocating above 4GB. 891 * 892 * XXX We guard this with _LP64 because vmem uses uintptr_t 893 * internally. 894 */ 895 if (!ok64) { 896 error = vmem_xalloc(r->arena, size, align, 0, 0, 897 VMEM_ADDR_MIN, 0xffffffffUL, 898 VM_BESTFIT | VM_NOSLEEP, 899 &result); 900 } else { 901 error = vmem_xalloc(r->arena, size, align, 0, 0, 902 (1UL << 32), VMEM_ADDR_MAX, 903 VM_BESTFIT | VM_NOSLEEP, 904 &result); 905 if (error) { 906 error = vmem_xalloc(r->arena, size, align, 0, 0, 907 VMEM_ADDR_MIN, VMEM_ADDR_MAX, 908 VM_BESTFIT | VM_NOSLEEP, 909 &result); 910 } 911 } 912 #else 913 error = vmem_xalloc(r->arena, size, align, 0, 0, 914 VMEM_ADDR_MIN, 0xffffffffUL, 915 VM_BESTFIT | VM_NOSLEEP, 916 &result); 917 #endif /* _L64 */ 918 919 if (error) 920 return ~0ULL; 921 922 return result; 923 } 924 925 static int 926 setup_iowins(pciconf_bus_t *pb) 927 { 928 pciconf_win_t *pi; 929 pciconf_dev_t *pd; 930 struct pciconf_resource_rsvd *rsvd; 931 int error; 932 933 for (pi = pb->pciiowin; pi < &pb->pciiowin[pb->niowin]; pi++) { 934 if (pi->size == 0) 935 continue; 936 937 pd = pi->dev; 938 rsvd = pci_bar_is_reserved(pb, pd, pi->reg); 939 940 if (pb->io_res.arena == NULL) { 941 /* Bus has no IO ranges, disable IO BAR */ 942 pi->address = 0; 943 pd->enable &= ~PCI_CONF_ENABLE_IO; 944 goto write_ioaddr; 945 } 946 947 pi->address = pci_allocate_range(&pb->io_res, pi->size, 948 pi->align, false); 949 if (~pi->address == 0) { 950 print_tag(pd->pc, pd->tag); 951 printf("Failed to allocate PCI I/O space (%" 952 PRIu64 " req)\n", pi->size); 953 return -1; 954 } 955 if (pd->ppb && pi->reg == 0) { 956 error = init_range_resource(&pd->ppb->io_res, 957 "ppb-io", pi->address, pi->size); 958 if (error) { 959 print_tag(pd->pc, pd->tag); 960 printf("Failed to alloc I/O arena for bus %d\n", 961 pd->ppb->busno); 962 return -1; 963 } 964 continue; 965 } 966 if (!pb->io_32bit && pi->address > 0xFFFF) { 967 pi->address = 0; 968 pd->enable &= ~PCI_CONF_ENABLE_IO; 969 } else { 970 pd->enable |= PCI_CONF_ENABLE_IO; 971 } 972 write_ioaddr: 973 if (pci_conf_debug) { 974 print_tag(pd->pc, pd->tag); 975 printf("Putting %" PRIu64 " I/O bytes @ %#" PRIx64 976 " (reg %x)\n", pi->size, pi->address, pi->reg); 977 } 978 pci_conf_write(pd->pc, pd->tag, pi->reg, 979 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 980 981 if (rsvd != NULL && rsvd->start != pi->address) 982 rsvd->callback(rsvd->callback_arg, pi->address); 983 } 984 return 0; 985 } 986 987 static int 988 setup_memwins(pciconf_bus_t *pb) 989 { 990 pciconf_win_t *pm; 991 pciconf_dev_t *pd; 992 pcireg_t base; 993 struct pciconf_resource *r; 994 struct pciconf_resource_rsvd *rsvd; 995 bool ok64; 996 int error; 997 998 for (pm = pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin]; pm++) { 999 if (pm->size == 0) 1000 continue; 1001 1002 ok64 = false; 1003 pd = pm->dev; 1004 rsvd = pci_bar_is_reserved(pb, pd, pm->reg); 1005 1006 if (pm->prefetch) { 1007 r = &pb->pmem_res; 1008 ok64 = pb->pmem_64bit; 1009 } else { 1010 r = &pb->mem_res; 1011 ok64 = pb->mem_64bit && pd->ppb == NULL; 1012 } 1013 1014 /* 1015 * We need to figure out if the memory BAR is 64-bit 1016 * capable or not. If it's not, then we need to constrain 1017 * the address allocation. 1018 */ 1019 if (PCICONF_MAPREG_IS_ROM(pm->reg)) { 1020 ok64 = false; 1021 } else if (ok64) { 1022 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 1023 ok64 = PCI_MAPREG_MEM_TYPE(base) == 1024 PCI_MAPREG_MEM_TYPE_64BIT; 1025 } 1026 1027 pm->address = pci_allocate_range(r, pm->size, pm->align, 1028 ok64); 1029 if (~pm->address == 0 && r == &pb->pmem_res) { 1030 r = &pb->mem_res; 1031 pm->address = pci_allocate_range(r, pm->size, 1032 pm->align, ok64); 1033 } 1034 if (~pm->address == 0) { 1035 print_tag(pd->pc, pd->tag); 1036 printf( 1037 "Failed to allocate PCI memory space (%" PRIu64 1038 " req, prefetch=%d ok64=%d)\n", pm->size, 1039 pm->prefetch, (int)ok64); 1040 return -1; 1041 } 1042 if (pd->ppb && pm->reg == 0) { 1043 const char *name = pm->prefetch ? "ppb-pmem" 1044 : "ppb-mem"; 1045 r = pm->prefetch ? &pd->ppb->pmem_res 1046 : &pd->ppb->mem_res; 1047 error = init_range_resource(r, name, 1048 pm->address, pm->size); 1049 if (error) { 1050 print_tag(pd->pc, pd->tag); 1051 printf("Failed to alloc MEM arena for bus %d\n", 1052 pd->ppb->busno); 1053 return -1; 1054 } 1055 continue; 1056 } 1057 if (!ok64 && pm->address > 0xFFFFFFFFULL) { 1058 pm->address = 0; 1059 pd->enable &= ~PCI_CONF_ENABLE_MEM; 1060 } else 1061 pd->enable |= PCI_CONF_ENABLE_MEM; 1062 1063 if (!PCICONF_MAPREG_IS_ROM(pm->reg)) { 1064 if (pci_conf_debug) { 1065 print_tag(pd->pc, pd->tag); 1066 printf( 1067 "Putting %" PRIu64 " MEM bytes @ %#" 1068 PRIx64 " (reg %x)\n", pm->size, 1069 pm->address, pm->reg); 1070 } 1071 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 1072 base = PCI_MAPREG_MEM_ADDR(pm->address) | 1073 PCI_MAPREG_MEM_TYPE(base); 1074 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 1075 if (PCI_MAPREG_MEM_TYPE(base) == 1076 PCI_MAPREG_MEM_TYPE_64BIT) { 1077 base = (pcireg_t) 1078 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 1079 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 1080 base); 1081 } 1082 } 1083 1084 if (rsvd != NULL && rsvd->start != pm->address) { 1085 /* 1086 * Resource allocation will never reuse a reserved 1087 * address. Check to see if the BAR is still reserved 1088 * to cover the case where the new resource was not 1089 * applied. In this case, there is no need to notify 1090 * the device callback of a change. 1091 */ 1092 if (!pci_bar_is_reserved(pb, pd, pm->reg)) { 1093 rsvd->callback(rsvd->callback_arg, pm->address); 1094 } 1095 } 1096 } 1097 for (pm = pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin]; pm++) { 1098 if (PCICONF_MAPREG_IS_ROM(pm->reg) && pm->address != -1) { 1099 pd = pm->dev; 1100 if (!(pd->enable & PCI_CONF_MAP_ROM)) 1101 continue; 1102 if (pci_conf_debug) { 1103 print_tag(pd->pc, pd->tag); 1104 printf( 1105 "Putting %" PRIu64 " ROM bytes @ %#" 1106 PRIx64 " (reg %x)\n", pm->size, 1107 pm->address, pm->reg); 1108 } 1109 base = (pcireg_t) pm->address; 1110 if (pd->enable & PCI_CONF_ENABLE_ROM) 1111 base |= PCI_MAPREG_ROM_ENABLE; 1112 1113 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 1114 } 1115 } 1116 return 0; 1117 } 1118 1119 static bool 1120 constrain_bridge_mem_range(struct pciconf_resource * const r, 1121 u_long * const base, 1122 u_long * const limit, 1123 const bool ok64 __used_only_lp64) 1124 { 1125 1126 *base = r->min_addr; 1127 *limit = r->max_addr; 1128 1129 #ifdef _LP64 1130 if (!ok64) { 1131 if (r->min_addr >= (1UL << 32)) { 1132 return true; 1133 } 1134 if (r->max_addr > 0xffffffffUL) { 1135 *limit = 0xffffffffUL; 1136 } 1137 } 1138 #endif /* _LP64 */ 1139 1140 return false; 1141 } 1142 1143 /* 1144 * Configure I/O, memory, and prefetcable memory spaces, then make 1145 * a call to configure_bus(). 1146 */ 1147 static int 1148 configure_bridge(pciconf_dev_t *pd) 1149 { 1150 unsigned long io_base, io_limit, mem_base, mem_limit; 1151 pciconf_bus_t *pb; 1152 pcireg_t io, iohigh, mem, cmd; 1153 int rv; 1154 bool isprefetchmem64; 1155 bool bad_range; 1156 1157 pb = pd->ppb; 1158 /* Configure I/O base & limit*/ 1159 if (pb->io_res.arena) { 1160 io_base = pb->io_res.min_addr; 1161 io_limit = pb->io_res.max_addr; 1162 } else { 1163 io_base = 0x1000; /* 4K */ 1164 io_limit = 0x0000; 1165 } 1166 if (pb->io_32bit) { 1167 iohigh = __SHIFTIN(io_base >> 16, PCI_BRIDGE_IOHIGH_BASE) | 1168 __SHIFTIN(io_limit >> 16, PCI_BRIDGE_IOHIGH_LIMIT); 1169 } else { 1170 if (io_limit > 0xFFFF) { 1171 printf("Bus %d bridge does not support 32-bit I/O. ", 1172 pb->busno); 1173 printf("Disabling I/O accesses\n"); 1174 io_base = 0x1000; /* 4K */ 1175 io_limit = 0x0000; 1176 } 1177 iohigh = 0; 1178 } 1179 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 1180 PCI_BRIDGE_STATIO_STATUS; 1181 io |= __SHIFTIN((io_base >> 8) & PCI_BRIDGE_STATIO_IOADDR, 1182 PCI_BRIDGE_STATIO_IOBASE); 1183 io |= __SHIFTIN((io_limit >> 8) & PCI_BRIDGE_STATIO_IOADDR, 1184 PCI_BRIDGE_STATIO_IOLIMIT); 1185 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 1186 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 1187 1188 /* Configure mem base & limit */ 1189 bad_range = false; 1190 if (pb->mem_res.arena) { 1191 bad_range = constrain_bridge_mem_range(&pb->mem_res, 1192 &mem_base, 1193 &mem_limit, 1194 false); 1195 } else { 1196 mem_base = 0x100000; /* 1M */ 1197 mem_limit = 0x000000; 1198 } 1199 if (bad_range) { 1200 printf("Bus %d bridge MEM range out of range. ", pb->busno); 1201 printf("Disabling MEM accesses\n"); 1202 mem_base = 0x100000; /* 1M */ 1203 mem_limit = 0x000000; 1204 } 1205 mem = __SHIFTIN((mem_base >> 16) & PCI_BRIDGE_MEMORY_ADDR, 1206 PCI_BRIDGE_MEMORY_BASE); 1207 mem |= __SHIFTIN((mem_limit >> 16) & PCI_BRIDGE_MEMORY_ADDR, 1208 PCI_BRIDGE_MEMORY_LIMIT); 1209 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 1210 1211 /* Configure prefetchable mem base & limit */ 1212 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 1213 isprefetchmem64 = PCI_BRIDGE_PREFETCHMEM_64BITS(mem); 1214 bad_range = false; 1215 if (pb->pmem_res.arena) { 1216 bad_range = constrain_bridge_mem_range(&pb->pmem_res, 1217 &mem_base, 1218 &mem_limit, 1219 isprefetchmem64); 1220 } else { 1221 mem_base = 0x100000; /* 1M */ 1222 mem_limit = 0x000000; 1223 } 1224 if (bad_range) { 1225 printf("Bus %d bridge does not support 64-bit PMEM. ", 1226 pb->busno); 1227 printf("Disabling prefetchable-MEM accesses\n"); 1228 mem_base = 0x100000; /* 1M */ 1229 mem_limit = 0x000000; 1230 } 1231 mem = __SHIFTIN((mem_base >> 16) & PCI_BRIDGE_PREFETCHMEM_ADDR, 1232 PCI_BRIDGE_PREFETCHMEM_BASE); 1233 mem |= __SHIFTIN((mem_limit >> 16) & PCI_BRIDGE_PREFETCHMEM_ADDR, 1234 PCI_BRIDGE_PREFETCHMEM_LIMIT); 1235 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 1236 /* 1237 * XXX -- 64-bit systems need a lot more than just this... 1238 */ 1239 if (isprefetchmem64) { 1240 mem_base = (uint64_t)mem_base >> 32; 1241 mem_limit = (uint64_t)mem_limit >> 32; 1242 pci_conf_write(pb->pc, pd->tag, 1243 PCI_BRIDGE_PREFETCHBASEUP32_REG, mem_base & 0xffffffff); 1244 pci_conf_write(pb->pc, pd->tag, 1245 PCI_BRIDGE_PREFETCHLIMITUP32_REG, mem_limit & 0xffffffff); 1246 } 1247 1248 rv = configure_bus(pb); 1249 1250 fini_range_resource(&pb->io_res); 1251 fini_range_resource(&pb->mem_res); 1252 fini_range_resource(&pb->pmem_res); 1253 1254 if (rv == 0) { 1255 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 1256 cmd &= ~PCI_BRIDGE_CONTROL; /* Clear control bit first */ 1257 cmd |= PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR; 1258 if (pb->fast_b2b) 1259 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B; 1260 1261 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 1262 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 1263 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 1264 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 1265 } 1266 1267 return rv; 1268 } 1269 1270 /* 1271 * Calculate latency values, allocate I/O and MEM segments, then set them 1272 * up. If a PCI-PCI bridge is found, configure the bridge separately, 1273 * which will cause a recursive call back here. 1274 */ 1275 static int 1276 configure_bus(pciconf_bus_t *pb) 1277 { 1278 pciconf_dev_t *pd; 1279 int def_ltim, max_ltim, band, bus_mhz; 1280 1281 if (pb->ndevs == 0) { 1282 if (pci_conf_debug) 1283 printf("PCI bus %d - no devices\n", pb->busno); 1284 return 1; 1285 } 1286 bus_mhz = pb->freq_66 ? 66 : 33; 1287 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 1288 band = 4000000; /* 0.25us cycles/sec */ 1289 if (band < pb->bandwidth_used) { 1290 printf("PCI bus %d: Warning: Total bandwidth exceeded!? (%d)\n", 1291 pb->busno, pb->bandwidth_used); 1292 def_ltim = -1; 1293 } else { 1294 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 1295 if (def_ltim > pb->min_maxlat) 1296 def_ltim = pb->min_maxlat; 1297 def_ltim = def_ltim * bus_mhz / 4; 1298 } 1299 def_ltim = (def_ltim + 7) & ~7; 1300 max_ltim = (max_ltim + 7) & ~7; 1301 1302 pb->def_ltim = MIN(def_ltim, 255); 1303 pb->max_ltim = MIN(MAX(max_ltim, def_ltim), 255); 1304 1305 /* 1306 * Now we have what we need to initialize the devices. 1307 * It would probably be better if we could allocate all of these 1308 * for all busses at once, but "not right now". First, get a list 1309 * of free memory ranges from the m.d. system. 1310 */ 1311 if (setup_iowins(pb) || setup_memwins(pb)) { 1312 printf("PCI bus configuration failed: " 1313 "unable to assign all I/O and memory ranges.\n"); 1314 return -1; 1315 } 1316 1317 /* 1318 * Configure the latency for the devices, and enable them. 1319 */ 1320 for (pd = pb->device; pd < &pb->device[pb->ndevs]; pd++) { 1321 pcireg_t cmd, classreg, misc; 1322 int ltim; 1323 1324 if (pci_conf_debug) { 1325 print_tag(pd->pc, pd->tag); 1326 printf("Configuring device.\n"); 1327 } 1328 classreg = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 1329 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 1330 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 1331 if (pd->enable & PCI_CONF_ENABLE_PARITY) 1332 cmd |= PCI_COMMAND_PARITY_ENABLE; 1333 if (pd->enable & PCI_CONF_ENABLE_SERR) 1334 cmd |= PCI_COMMAND_SERR_ENABLE; 1335 if (pb->fast_b2b) 1336 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 1337 if (PCI_CLASS(classreg) != PCI_CLASS_BRIDGE || 1338 PCI_SUBCLASS(classreg) != PCI_SUBCLASS_BRIDGE_PCI) { 1339 if (pd->enable & PCI_CONF_ENABLE_IO) 1340 cmd |= PCI_COMMAND_IO_ENABLE; 1341 if (pd->enable & PCI_CONF_ENABLE_MEM) 1342 cmd |= PCI_COMMAND_MEM_ENABLE; 1343 if (pd->enable & PCI_CONF_ENABLE_BM) 1344 cmd |= PCI_COMMAND_MASTER_ENABLE; 1345 ltim = pd->min_gnt * bus_mhz / 4; 1346 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 1347 } else { 1348 cmd |= PCI_COMMAND_MASTER_ENABLE; 1349 ltim = MIN (pb->def_ltim, pb->max_ltim); 1350 } 1351 if ((pd->enable & 1352 (PCI_CONF_ENABLE_MEM | PCI_CONF_ENABLE_IO)) == 0) { 1353 print_tag(pd->pc, pd->tag); 1354 printf("Disabled due to lack of resources.\n"); 1355 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 1356 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 1357 } 1358 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 1359 1360 misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 1361 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 1362 misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT; 1363 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) << 1364 PCI_CACHELINE_SHIFT; 1365 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 1366 1367 if (pd->ppb) { 1368 if (configure_bridge(pd) < 0) 1369 return -1; 1370 continue; 1371 } 1372 } 1373 1374 if (pci_conf_debug) 1375 printf("PCI bus %d configured\n", pb->busno); 1376 1377 return 0; 1378 } 1379 1380 static bool 1381 mem_region_ok64(struct pciconf_resource * const r __used_only_lp64) 1382 { 1383 bool rv = false; 1384 1385 #ifdef _LP64 1386 /* 1387 * XXX We need to guard this with _LP64 because vmem uses 1388 * uintptr_t internally. 1389 */ 1390 vmem_size_t result; 1391 if (vmem_xalloc(r->arena, 1/*size*/, 1/*align*/, 0/*phase*/, 1392 0/*nocross*/, (1UL << 32), VMEM_ADDR_MAX, 1393 VM_INSTANTFIT | VM_NOSLEEP, &result) == 0) { 1394 vmem_free(r->arena, result, 1); 1395 rv = true; 1396 } 1397 #endif /* _LP64 */ 1398 1399 return rv; 1400 } 1401 1402 /* 1403 * pciconf_resource_init: 1404 * 1405 * Allocate and initialize a pci configuration resources container. 1406 */ 1407 struct pciconf_resources * 1408 pciconf_resource_init(void) 1409 { 1410 struct pciconf_resources *rs; 1411 1412 rs = kmem_zalloc(sizeof(*rs), KM_SLEEP); 1413 1414 return rs; 1415 } 1416 1417 /* 1418 * pciconf_resource_fini: 1419 * 1420 * Dispose of a pci configuration resources container. 1421 */ 1422 void 1423 pciconf_resource_fini(struct pciconf_resources *rs) 1424 { 1425 int i; 1426 1427 for (i = 0; i < PCICONF_RESOURCE_NTYPES; i++) { 1428 fini_range_resource(&rs->resources[i]); 1429 } 1430 1431 kmem_free(rs, sizeof(*rs)); 1432 } 1433 1434 /* 1435 * pciconf_resource_add: 1436 * 1437 * Add a pci configuration resource to a container. 1438 */ 1439 int 1440 pciconf_resource_add(struct pciconf_resources *rs, int type, 1441 bus_addr_t start, bus_size_t size) 1442 { 1443 bus_addr_t end = start + (size - 1); 1444 struct pciconf_resource *r; 1445 struct pciconf_resource_rsvd *rsvd; 1446 int error, rsvd_type, align; 1447 vmem_addr_t result; 1448 bool first; 1449 1450 if (size == 0 || end <= start) 1451 return EINVAL; 1452 1453 if (type < 0 || type >= PCICONF_RESOURCE_NTYPES) 1454 return EINVAL; 1455 1456 r = &rs->resources[type]; 1457 1458 first = r->arena == NULL; 1459 if (first) { 1460 r->arena = create_vmem_arena(pciconf_resource_names[type], 1461 0, 0, VM_SLEEP); 1462 r->min_addr = VMEM_ADDR_MAX; 1463 r->max_addr = VMEM_ADDR_MIN; 1464 } 1465 1466 error = vmem_add(r->arena, start, size, VM_SLEEP); 1467 if (error == 0) { 1468 if (start < r->min_addr) 1469 r->min_addr = start; 1470 if (end > r->max_addr) 1471 r->max_addr = end; 1472 } 1473 1474 r->total_size += size; 1475 1476 switch (type) { 1477 case PCICONF_RESOURCE_IO: 1478 rsvd_type = PCI_CONF_MAP_IO; 1479 align = 0x1000; 1480 break; 1481 case PCICONF_RESOURCE_MEM: 1482 case PCICONF_RESOURCE_PREFETCHABLE_MEM: 1483 rsvd_type = PCI_CONF_MAP_MEM; 1484 align = 0x100000; 1485 break; 1486 default: 1487 rsvd_type = 0; 1488 align = 0; 1489 break; 1490 } 1491 1492 /* 1493 * Exclude reserved ranges from available resources 1494 */ 1495 LIST_FOREACH(rsvd, &pciconf_resource_reservations, next) { 1496 if (rsvd->type != rsvd_type) 1497 continue; 1498 /* 1499 * The reserved range may not be within our resource window. 1500 * That's fine, so ignore the error. 1501 */ 1502 (void)vmem_xalloc(r->arena, rsvd->size, align, 0, 0, 1503 rsvd->start, rsvd->start + rsvd->size, 1504 VM_BESTFIT | VM_NOSLEEP, 1505 &result); 1506 } 1507 1508 return 0; 1509 } 1510 1511 /* 1512 * pciconf_resource_reserve: 1513 * 1514 * Mark a pci configuration resource as in-use. Devices 1515 * already configured to use these resources are notified 1516 * during resource assignment if their resources are changed. 1517 */ 1518 void 1519 pciconf_resource_reserve(int type, bus_addr_t start, bus_size_t size, 1520 void (*callback)(void *, uint64_t), void *callback_arg) 1521 { 1522 struct pciconf_resource_rsvd *rsvd; 1523 1524 rsvd = kmem_zalloc(sizeof(*rsvd), KM_SLEEP); 1525 rsvd->type = type; 1526 rsvd->start = start; 1527 rsvd->size = size; 1528 rsvd->callback = callback; 1529 rsvd->callback_arg = callback_arg; 1530 LIST_INSERT_HEAD(&pciconf_resource_reservations, rsvd, next); 1531 } 1532 1533 /* 1534 * Let's configure the PCI bus. 1535 * This consists of basically scanning for all existing devices, 1536 * identifying their needs, and then making another pass over them 1537 * to set: 1538 * 1. I/O addresses 1539 * 2. Memory addresses (Prefetchable and not) 1540 * 3. PCI command register 1541 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1542 * Header type, Latency timer, Cache line size) register 1543 * 1544 * The command register is set to enable fast back-to-back transactions 1545 * if the host bridge says it can handle it. We also configure 1546 * Master Enable, SERR enable, parity enable, and (if this is not a 1547 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1548 * will not report some I/O space. 1549 * 1550 * The latency is computed to be a "fair share" of the bus bandwidth. 1551 * The bus bandwidth variable is initialized to the number of PCI cycles 1552 * in one second. The number of cycles taken for one transaction by each 1553 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1554 * Care is taken to ensure that the latency timer won't be set such that 1555 * it would exceed the critical time for any device. 1556 * 1557 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1558 * bridges are probed and configured recursively. 1559 */ 1560 int 1561 pci_configure_bus(pci_chipset_tag_t pc, struct pciconf_resources *rs, 1562 int firstbus, int cacheline_size) 1563 { 1564 pciconf_bus_t *pb; 1565 int rv; 1566 1567 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_SLEEP); 1568 pb->busno = firstbus; 1569 pb->next_busno = pb->busno + 1; 1570 pb->last_busno = 255; 1571 pb->cacheline_size = cacheline_size; 1572 pb->parent_bus = NULL; 1573 pb->swiz = 0; 1574 pb->io_32bit = 1; 1575 pb->io_res = rs->resources[PCICONF_RESOURCE_IO]; 1576 1577 pb->mem_res = rs->resources[PCICONF_RESOURCE_MEM]; 1578 if (pb->mem_res.arena == NULL) 1579 pb->mem_res = rs->resources[PCICONF_RESOURCE_PREFETCHABLE_MEM]; 1580 1581 pb->pmem_res = rs->resources[PCICONF_RESOURCE_PREFETCHABLE_MEM]; 1582 if (pb->pmem_res.arena == NULL) 1583 pb->pmem_res = rs->resources[PCICONF_RESOURCE_MEM]; 1584 1585 /* 1586 * Probe the memory region arenas to see if allocation of 1587 * 64-bit addresses is possible. 1588 */ 1589 pb->mem_64bit = mem_region_ok64(&pb->mem_res); 1590 pb->pmem_64bit = mem_region_ok64(&pb->pmem_res); 1591 1592 pb->pc = pc; 1593 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1594 1595 rv = probe_bus(pb); 1596 pb->last_busno = pb->next_busno - 1; 1597 if (rv == 0) 1598 rv = configure_bus(pb); 1599 1600 /* 1601 * All done! 1602 */ 1603 kmem_free(pb, sizeof(*pb)); 1604 return rv; 1605 } 1606
Indexes created Mon Sep 28 00:25:45 UTC 2026