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    Searched refs:pcie_speed_table (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu7_hwmgr.c 563 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
574 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
580 data->dpm_table.pcie_speed_table.count = max_entry - 1;
584 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
589 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
594 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
599 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
604 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
609 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
615 data->dpm_table.pcie_speed_table.count = 6
    [all...]
smu7_hwmgr.h 108 struct smu7_single_dpm_table pcie_speed_table; member in struct:smu7_dpm_table
  /src/sys/external/bsd/drm2/dist/drm/radeon/
ci_dpm.h 73 struct ci_single_dpm_table pcie_speed_table; member in struct:ci_dpm_table
radeon_ci_dpm.c 2639 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2641 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2643 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2649 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2651 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
3415 &pi->dpm_table.pcie_speed_table,
3419 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3423 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3426 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3429 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_vegam_smumgr.c 581 /* Index (dpm_table->pcie_speed_table.count)
583 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
585 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
587 dpm_table->pcie_speed_table.dpm_levels[i].param1);
595 (uint8_t)dpm_table->pcie_speed_table.count;
599 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
874 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
2036 PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1,
2040 hw_data->dpm_table.pcie_speed_table.count;
2105 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++)
    [all...]
amdgpu_fiji_smumgr.c 841 /* Index (dpm_table->pcie_speed_table.count)
843 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
845 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
847 dpm_table->pcie_speed_table.dpm_levels[i].param1);
855 (uint8_t)dpm_table->pcie_speed_table.count;
857 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1015 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
amdgpu_tonga_smumgr.c 519 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
520 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
522 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
524 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
536 (uint8_t)dpm_table->pcie_speed_table.count;
538 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
698 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
2351 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
2355 table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
amdgpu_iceland_smumgr.c 776 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
777 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
779 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
781 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
793 (uint8_t)dpm_table->pcie_speed_table.count;
795 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
amdgpu_ci_smumgr.c 1007 /* Index dpm_table->pcie_speed_table.count is reserved for PCIE boot level.*/
1008 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1010 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1012 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
1019 (uint8_t)dpm_table->pcie_speed_table.count;
1021 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2057 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
2061 table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count;
amdgpu_polaris10_smumgr.c 779 /* Index (dpm_table->pcie_speed_table.count)
781 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
783 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
785 dpm_table->pcie_speed_table.dpm_levels[i].param1);
793 (uint8_t)dpm_table->pcie_speed_table.count;
797 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
990 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
1993 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {

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