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    Searched refs:phy_reg (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/arch/arm/sunxi/
sunxi_usb3phy.c 78 struct fdtbus_regulator *phy_reg; member in struct:sunxi_usb3phy
146 return phy->phy_reg ? fdtbus_regulator_enable(phy->phy_reg) : 0;
148 return phy->phy_reg ? fdtbus_regulator_disable(phy->phy_reg) : 0;
194 phy->phy_reg = fdtbus_regulator_acquire(phandle, "phy-supply");
sunxi_usbphy.c 107 struct fdtbus_regulator *phy_reg; member in struct:sunxi_usbphy
318 if (phy->phy_reg == NULL)
325 return fdtbus_regulator_enable(phy->phy_reg);
327 return fdtbus_regulator_disable(phy->phy_reg);
384 phy->phy_reg = fdtbus_regulator_acquire(phandle, pname);
  /src/sys/arch/mips/ralink/
ralink_eth.c 1682 ralink_eth_mii_read(device_t self, int phy_addr, int phy_reg, uint16_t *val)
1687 printf("%s() phy_addr: %d phy_reg: %d\n", __func__, phy_addr, phy_reg);
1714 PCTL0_RD_CMD | PCTL0_REG(phy_reg) | PCTL0_ADDR(phy_addr));
1717 MDIO_ACCESS_PHY_ADDR(phy_addr) | MDIO_ACCESS_REG(phy_reg));
1719 MDIO_ACCESS_PHY_ADDR(phy_addr) | MDIO_ACCESS_REG(phy_reg) |
1750 ralink_eth_mii_write(device_t self, int phy_addr, int phy_reg, uint16_t val)
1755 printf("%s() phy_addr: %d phy_reg: %d val: 0x%04x\n",
1756 __func__, phy_addr, phy_reg, val);
1776 PCTL0_WR_CMD | PCTL0_WR_VAL(val) | PCTL0_REG(phy_reg) |
    [all...]
  /src/sys/dev/pci/
if_wm.c 10583 uint16_t phy_reg; local in function:wm_linkintr_gmii
10586 I217_PLL_CLOCK_GATE_REG, &phy_reg);
10587 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
10590 phy_reg |= 0x3e8;
10592 phy_reg |= 0xfa;
10594 I217_PLL_CLOCK_GATE_REG, phy_reg);
10598 HV_PM_CTRL, &phy_reg);
10600 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
10603 HV_PM_CTRL, phy_reg);
12577 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_RE
16679 uint16_t anar, phy_reg; local in function:wm_suspend_workarounds_ich8lan
16763 uint16_t phy_reg; local in function:wm_resume_workarounds_pchlan
    [all...]

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