1 /* $NetBSD: sunxi_usbphy.c,v 1.18 2024/08/13 07:20:23 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: sunxi_usbphy.c,v 1.18 2024/08/13 07:20:23 skrll Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 /* PHY control registers */ 43 #define PHYCTL_ICR 0x00 44 #define PHYCTL_ICR_ID_PULLUP __BIT(17) 45 #define PHYCTL_ICR_DPDM_PULLUP __BIT(16) 46 #define PHYCTL_ICR_FORCE_ID __BITS(15,14) 47 #define PHYCTL_ICR_FORCE_ID_LOW 2 48 #define PHYCTL_ICR_FORCE_ID_HIGH 3 49 #define PHYCTL_ICR_FORCE_VBUS __BITS(13,12) 50 #define PHYCTL_ICR_FORCE_VBUS_LOW 2 51 #define PHYCTL_ICR_FORCE_VBUS_HIGH 3 52 #define PHYCTL_A10 0x04 53 #define PHYCTL_A33 0x10 54 #define PHYCTL_ADDR __BITS(15,8) 55 #define PHYCTL_DATA __BIT(7) 56 #define PHYCTL_OTG_CFG 0x20 57 #define PHYCTL_OTG_ROUTE_OTG __BIT(0) 58 59 /* PHY registers */ 60 #define PHY_RES45_CAL_EN 0x0c 61 #define PHY_TX_AMPLITUDE_TUNE 0x20 62 #define PHY_DISCON_TH_SEL 0x2a 63 64 /* PMU registers */ 65 #define PMU_CFG 0x00 66 #define AHB_INCR8 __BIT(10) 67 #define AHB_INCR4 __BIT(9) 68 #define AHB_INCRX_ALIGN __BIT(8) 69 #define ULPI_BYPASS __BIT(0) 70 #define PMU_UNK_H3 0x10 71 #define PMU_UNK_H3_CLR __BIT(1) 72 73 static int sunxi_usbphy_match(device_t, cfdata_t, void *); 74 static void sunxi_usbphy_attach(device_t, device_t, void *); 75 76 enum sunxi_usbphy_type { 77 USBPHY_A10 = 1, 78 USBPHY_A13, 79 USBPHY_A20, 80 USBPHY_A31, 81 USBPHY_A64, 82 USBPHY_A83T, 83 USBPHY_D1, 84 USBPHY_H3, 85 USBPHY_H6, 86 }; 87 88 static const struct device_compatible_entry compat_data[] = { 89 { .compat = "allwinner,sun4i-a10-usb-phy", .value = USBPHY_A10 }, 90 { .compat = "allwinner,sun5i-a13-usb-phy", .value = USBPHY_A13 }, 91 { .compat = "allwinner,sun6i-a31-usb-phy", .value = USBPHY_A31 }, 92 { .compat = "allwinner,sun7i-a20-usb-phy", .value = USBPHY_A20 }, 93 { .compat = "allwinner,sun8i-a83t-usb-phy", .value = USBPHY_A83T }, 94 { .compat = "allwinner,sun8i-h3-usb-phy", .value = USBPHY_H3 }, 95 { .compat = "allwinner,sun8i-v3s-usb-phy", .value = USBPHY_H3 }, 96 { .compat = "allwinner,sun20i-d1-usb-phy", .value = USBPHY_D1 }, 97 { .compat = "allwinner,sun50i-a64-usb-phy", .value = USBPHY_A64 }, 98 { .compat = "allwinner,sun50i-h6-usb-phy", .value = USBPHY_H6 }, 99 DEVICE_COMPAT_EOL 100 }; 101 102 #define SUNXI_MAXUSBPHY 4 103 104 struct sunxi_usbphy { 105 u_int phy_index; 106 bus_space_handle_t phy_bsh; 107 struct fdtbus_regulator *phy_reg; 108 }; 109 110 struct sunxi_usbphy_softc { 111 device_t sc_dev; 112 bus_space_tag_t sc_bst; 113 bus_space_handle_t sc_bsh_phy_ctrl; 114 enum sunxi_usbphy_type sc_type; 115 116 struct sunxi_usbphy sc_phys[SUNXI_MAXUSBPHY]; 117 u_int sc_nphys; 118 119 struct fdtbus_gpio_pin *sc_gpio_id_det; 120 struct fdtbus_gpio_pin *sc_gpio_vbus_det; 121 }; 122 123 #define PHYCTL_READ(sc, reg) \ 124 bus_space_read_4((sc)->sc_bst, \ 125 (sc)->sc_bsh_phy_ctrl, (reg)) 126 #define PHYCTL_WRITE(sc, reg, val) \ 127 bus_space_write_4((sc)->sc_bst, \ 128 (sc)->sc_bsh_phy_ctrl, (reg), (val)) 129 #define PMU_READ(sc, id, reg) \ 130 bus_space_read_4((sc)->sc_bst, \ 131 (sc)->sc_phys[(id)].phy_bsh, (reg)) 132 #define PMU_WRITE(sc, id, reg, val) \ 133 bus_space_write_4((sc)->sc_bst, \ 134 (sc)->sc_phys[(id)].phy_bsh, (reg), (val)) 135 136 CFATTACH_DECL_NEW(sunxi_usbphy, sizeof(struct sunxi_usbphy_softc), 137 sunxi_usbphy_match, sunxi_usbphy_attach, NULL, NULL); 138 139 static void 140 sunxi_usbphy_write(struct sunxi_usbphy_softc *sc, 141 struct sunxi_usbphy *phy, u_int bit_addr, u_int bits, 142 u_int len) 143 { 144 const uint32_t usbc_mask = __BIT(phy->phy_index * 2); 145 bus_size_t reg; 146 uint32_t val; 147 148 switch (sc->sc_type) { 149 case USBPHY_A10: 150 case USBPHY_A13: 151 case USBPHY_A20: 152 case USBPHY_A31: 153 reg = PHYCTL_A10; 154 break; 155 case USBPHY_D1: 156 case USBPHY_H3: 157 case USBPHY_H6: 158 case USBPHY_A64: 159 case USBPHY_A83T: 160 reg = PHYCTL_A33; 161 break; 162 default: 163 panic("unsupported phy type"); 164 } 165 166 if (reg == PHYCTL_A33) 167 PHYCTL_WRITE(sc, reg, 0); 168 169 for (; len > 0; bit_addr++, bits >>= 1, len--) { 170 val = PHYCTL_READ(sc, reg); 171 val &= ~PHYCTL_ADDR; 172 val |= __SHIFTIN(bit_addr, PHYCTL_ADDR); 173 PHYCTL_WRITE(sc, reg, val); 174 175 val = PHYCTL_READ(sc, reg); 176 val &= ~PHYCTL_DATA; 177 val |= __SHIFTIN(bits & 1, PHYCTL_DATA); 178 PHYCTL_WRITE(sc, reg, val); 179 180 PHYCTL_READ(sc, reg); 181 val |= usbc_mask; 182 PHYCTL_WRITE(sc, reg, val); 183 184 PHYCTL_READ(sc, reg); 185 val &= ~usbc_mask; 186 PHYCTL_WRITE(sc, reg, val); 187 } 188 } 189 190 static bool 191 sunxi_usbphy_vbus_detect(struct sunxi_usbphy_softc *sc) 192 { 193 if (sc->sc_gpio_vbus_det) 194 return fdtbus_gpio_read(sc->sc_gpio_vbus_det); 195 return 1; 196 } 197 198 static void * 199 sunxi_usbphy_acquire(device_t dev, const void *data, size_t len) 200 { 201 struct sunxi_usbphy_softc * const sc = device_private(dev); 202 203 if (len != 4) 204 return NULL; 205 206 const int phy_id = be32dec(data); 207 if (phy_id >= sc->sc_nphys || !sc->sc_phys[phy_id].phy_bsh) 208 return NULL; 209 210 return &sc->sc_phys[phy_id]; 211 } 212 213 static void 214 sunxi_usbphy_release(device_t dev, void *priv) 215 { 216 } 217 218 static int 219 sunxi_usbphy_enable(device_t dev, void *priv, bool enable) 220 { 221 struct sunxi_usbphy_softc * const sc = device_private(dev); 222 struct sunxi_usbphy * const phy = priv; 223 u_int disc_thresh; 224 bool phy0_reroute; 225 uint32_t val; 226 227 switch (sc->sc_type) { 228 case USBPHY_A13: 229 disc_thresh = 0x2; 230 phy0_reroute = false; 231 break; 232 case USBPHY_A10: 233 case USBPHY_A20: 234 case USBPHY_A31: 235 disc_thresh = 0x3; 236 phy0_reroute = false; 237 break; 238 case USBPHY_A64: 239 case USBPHY_D1: 240 case USBPHY_H3: 241 case USBPHY_H6: 242 disc_thresh = 0x3; 243 phy0_reroute = true; 244 break; 245 case USBPHY_A83T: 246 disc_thresh = 0x0; 247 phy0_reroute = false; 248 break; 249 default: 250 aprint_error_dev(dev, "unsupported board\n"); 251 return ENXIO; 252 } 253 254 if (phy->phy_bsh) { 255 /* Enable/disable passby */ 256 const uint32_t mask = 257 ULPI_BYPASS|AHB_INCR8|AHB_INCR4|AHB_INCRX_ALIGN; 258 val = PMU_READ(sc, phy->phy_index, PMU_CFG); 259 if (enable) 260 val |= mask; 261 else 262 val &= ~mask; 263 PMU_WRITE(sc, phy->phy_index, PMU_CFG, val); 264 } 265 266 switch (sc->sc_type) { 267 case USBPHY_H3: 268 case USBPHY_A64: 269 if (enable && phy->phy_bsh) { 270 val = PMU_READ(sc, phy->phy_index, PMU_UNK_H3); 271 val &= ~PMU_UNK_H3_CLR; 272 PMU_WRITE(sc, phy->phy_index, PMU_UNK_H3, val); 273 } 274 break; 275 default: 276 break; 277 } 278 279 if (enable) { 280 switch (sc->sc_type) { 281 case USBPHY_A83T: 282 case USBPHY_H6: 283 break; 284 default: 285 if (phy->phy_index == 0) 286 sunxi_usbphy_write(sc, phy, PHY_RES45_CAL_EN, 0x1, 1); 287 sunxi_usbphy_write(sc, phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5); 288 sunxi_usbphy_write(sc, phy, PHY_DISCON_TH_SEL, disc_thresh, 2); 289 break; 290 } 291 } 292 293 if (phy->phy_index == 0) { 294 const uint32_t mask = 295 PHYCTL_ICR_ID_PULLUP|PHYCTL_ICR_DPDM_PULLUP; 296 val = PHYCTL_READ(sc, PHYCTL_ICR); 297 298 if (enable) 299 val |= mask; 300 else 301 val &= ~mask; 302 303 /* XXX only host mode is supported */ 304 val &= ~PHYCTL_ICR_FORCE_ID; 305 val |= __SHIFTIN(PHYCTL_ICR_FORCE_ID_LOW, PHYCTL_ICR_FORCE_ID); 306 val &= ~PHYCTL_ICR_FORCE_VBUS; 307 val |= __SHIFTIN(PHYCTL_ICR_FORCE_VBUS_HIGH, PHYCTL_ICR_FORCE_VBUS); 308 309 PHYCTL_WRITE(sc, PHYCTL_ICR, val); 310 311 if (phy0_reroute) { 312 val = PHYCTL_READ(sc, PHYCTL_OTG_CFG); 313 val &= ~PHYCTL_OTG_ROUTE_OTG; 314 PHYCTL_WRITE(sc, PHYCTL_OTG_CFG, val); 315 } 316 } 317 318 if (phy->phy_reg == NULL) 319 return 0; 320 321 if (enable) { 322 /* If an external vbus is detected, do not enable phy 0 */ 323 if (phy->phy_index == 0 && sunxi_usbphy_vbus_detect(sc)) 324 return 0; 325 return fdtbus_regulator_enable(phy->phy_reg); 326 } else { 327 return fdtbus_regulator_disable(phy->phy_reg); 328 } 329 } 330 331 const struct fdtbus_phy_controller_func sunxi_usbphy_funcs = { 332 .acquire = sunxi_usbphy_acquire, 333 .release = sunxi_usbphy_release, 334 .enable = sunxi_usbphy_enable, 335 }; 336 337 static int 338 sunxi_usbphy_match(device_t parent, cfdata_t cf, void *aux) 339 { 340 struct fdt_attach_args * const faa = aux; 341 342 return of_compatible_match(faa->faa_phandle, compat_data); 343 } 344 345 static void 346 sunxi_usbphy_attach(device_t parent, device_t self, void *aux) 347 { 348 struct sunxi_usbphy_softc * const sc = device_private(self); 349 struct fdt_attach_args * const faa = aux; 350 const int phandle = faa->faa_phandle; 351 struct fdtbus_reset *rst; 352 struct sunxi_usbphy *phy; 353 struct clk *clk; 354 bus_addr_t addr; 355 bus_size_t size; 356 char pname[20]; 357 u_int n; 358 359 sc->sc_dev = self; 360 sc->sc_bst = faa->faa_bst; 361 sc->sc_type = of_compatible_lookup(phandle, compat_data)->value; 362 363 if (fdtbus_get_reg_byname(phandle, "phy_ctrl", &addr, &size) != 0) { 364 aprint_error(": couldn't get phy ctrl registers\n"); 365 return; 366 } 367 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh_phy_ctrl) != 0) { 368 aprint_error(": couldn't map phy ctrl registers\n"); 369 return; 370 } 371 372 for (sc->sc_nphys = 0; sc->sc_nphys < SUNXI_MAXUSBPHY; sc->sc_nphys++) { 373 phy = &sc->sc_phys[sc->sc_nphys]; 374 phy->phy_index = sc->sc_nphys; 375 snprintf(pname, sizeof(pname), "pmu%d", sc->sc_nphys); 376 if (fdtbus_get_reg_byname(phandle, pname, &addr, &size) != 0) { 377 continue; 378 } else if (bus_space_map(sc->sc_bst, addr, size, 0, &phy->phy_bsh) != 0) { 379 aprint_error(": failed to map reg #%d\n", sc->sc_nphys); 380 return; 381 } 382 /* Get optional regulator */ 383 snprintf(pname, sizeof(pname), "usb%d_vbus-supply", sc->sc_nphys); 384 phy->phy_reg = fdtbus_regulator_acquire(phandle, pname); 385 } 386 387 /* Enable clocks */ 388 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) 389 if (clk_enable(clk) != 0) { 390 aprint_error(": couldn't enable clock #%d\n", n); 391 return; 392 } 393 /* De-assert resets */ 394 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) 395 if (fdtbus_reset_deassert(rst) != 0) { 396 aprint_error(": couldn't de-assert reset #%d\n", n); 397 return; 398 } 399 400 aprint_naive("\n"); 401 aprint_normal(": USB PHY\n"); 402 403 fdtbus_register_phy_controller(self, phandle, &sunxi_usbphy_funcs); 404 } 405
Indexes created Sun Sep 21 19:09:51 GMT 2025