| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/basics/ |
| dc_common.h | 35 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
37 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
39 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
|
| amdgpu_dc_common.c | 57 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
59 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
61 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
66 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
68 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_hwseq.h | 34 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
36 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
40 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
41 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
42 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
[all...] |
| amdgpu_dcn20_hwseq.c | 93 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
98 struct pipe_ctx *pipe_ctx,
110 if (pipe_ctx->stream_res.gsl_group > 0)
115 pipe_ctx->stream_res.gsl_group = group_idx;
137 group_idx = pipe_ctx->stream_res.gsl_group;
141 pipe_ctx->stream_res.gsl_group = 0;
165 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
166 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
167 pipe_ctx->stream_res.tg->funcs->set_gsl
1578 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
1627 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
1716 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
2095 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
2352 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
2389 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
[all...] |
| dcn20_resource.h | 56 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
136 struct pipe_ctx *primary_pipe,
137 struct pipe_ctx *secondary_pipe);
141 struct pipe_ctx *prev_odm_pipe,
142 struct pipe_ctx *next_odm_pipe);
143 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
146 const struct pipe_ctx *primary_pipe);
|
| amdgpu_dcn20_resource.c | 1445 struct pipe_ctx *pipe_ctx,
1448 const struct dc_stream_state *stream = pipe_ctx->stream;
1449 struct pipe_ctx *odm_pipe;
1452 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1457 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1458 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1488 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1491 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params)
1510 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); local
1591 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; local
1617 struct pipe_ctx *pipe_ctx = NULL; local
2291 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| dce110_hw_sequencer.h | 45 void dce110_enable_stream(struct pipe_ctx *pipe_ctx);
47 void dce110_disable_stream(struct pipe_ctx *pipe_ctx);
49 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
52 void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
54 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
[all...] |
| amdgpu_dce110_hw_sequencer.c | 278 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
281 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
606 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
609 struct transform *xfm = pipe_ctx->plane_res.xfm;
631 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
636 ASSERT(pipe_ctx->stream);
638 if (pipe_ctx->stream_res.stream_enc == NULL
1643 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
1787 struct pipe_ctx *pipe_ctx = NULL; local
1856 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; local
1881 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
1966 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
1994 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
2045 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
2070 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
2583 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
2594 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
2616 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
[all...] |
| dce110_resource.h | 43 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);
|
| amdgpu_dce110_resource.c | 861 const struct pipe_ctx *pipe_ctx,
864 const struct dc_stream_state *stream = pipe_ctx->stream;
872 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
873 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
895 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
897 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
898 pipe_ctx->clock_source->funcs->get_pix_clk_dividers
923 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); local
1108 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| hw_sequencer.h | 42 struct pipe_ctx;
65 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
72 struct pipe_ctx *pipe_ctx);
77 struct pipe_ctx *pipe_ctx);
79 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);
80 void (*update_pending_status)(struct pipe_ctx *pipe_ctx)
[all...] |
| hw_sequencer_private.h | 51 struct pipe_ctx;
71 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
72 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
76 struct pipe_ctx *pipe_ctx);
78 struct pipe_ctx *pipe_ctx);
79 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx)
[all...] |
| dc_link_dp.h | 65 struct pipe_ctx *pipe_ctx,
85 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
86 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
87 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
88 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
[all...] |
| resource.h | 92 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
98 void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
121 struct pipe_ctx *pipe_ctx);
127 struct pipe_ctx *resource_get_head_pipe_for_stream(
138 struct pipe_ctx *find_idle_secondary_pipe(
141 const struct pipe_ctx *primary_pipe);
168 struct pipe_ctx *pipe_ctx_old
[all...] |
| core_types.h | 80 struct pipe_ctx *pipe_ctx);
82 void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
84 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
113 struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
278 struct pipe_ctx { struct
291 struct pipe_ctx *top_pipe;
292 struct pipe_ctx *bottom_pipe
308 struct pipe_ctx pipe_ctx[MAX_PIPES]; member in struct:resource_context
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| dcn10_hw_sequencer.h | 38 int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
39 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
41 struct pipe_ctx *pipe_ctx,
52 struct pipe_ctx *pipe,
56 struct pipe_ctx *pipe_ctx,
58 void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx
[all...] |
| amdgpu_dcn10_hw_sequencer.c | 94 struct pipe_ctx *pipe_ctx; local
99 pipe_ctx = &context->res_ctx.pipe_ctx[i];
100 tg = pipe_ctx->stream_res.tg;
105 if (pipe_ctx->top_pipe ||
106 !pipe_ctx->stream || !pipe_ctx->plane_state ||
466 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
938 struct pipe_ctx *pipe_ctx = local
963 struct pipe_ctx *pipe_ctx = local
976 struct pipe_ctx *pipe_ctx = local
986 struct pipe_ctx *pipe_ctx = local
998 struct pipe_ctx *pipe_ctx = local
1147 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
1173 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
1187 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
1382 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
2494 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
2557 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
2594 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_resource.c | 421 const struct pipe_ctx *pipe_with_clk_src,
422 const struct pipe_ctx *pipe)
453 struct pipe_ctx *pipe_ctx)
458 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
459 return res_ctx->pipe_ctx[i].clock_source;
540 static void calculate_viewport(struct pipe_ctx *pipe_ctx)
542 const struct dc_plane_state *plane_state = pipe_ctx->plane_state
1361 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
1644 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; local
1915 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; local
1962 struct pipe_ctx *pipe_ctx = NULL; local
2111 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; local
2594 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( local
[all...] |
| amdgpu_dc_link_hwss.c | 106 struct pipe_ctx *pipes =
107 link->dc->current_state->res_ctx.pipe_ctx;
315 struct pipe_ctx *pipes =
316 &link->dc->current_state->res_ctx.pipe_ctx[0];
400 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
402 struct dc *dc = pipe_ctx->stream->ctx->dc;
403 struct dc_stream_state *stream = pipe_ctx->stream;
416 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable
[all...] |
| amdgpu_dc_link.c | 1467 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1469 struct dc_stream_state *stream = pipe_ctx->stream;
1490 struct pipe_ctx *pipe_ctx)
1492 struct dc_stream_state *stream = pipe_ctx->stream;
1512 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1518 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1532 pipe_ctx,
1533 pipe_ctx->stream->signal))
2878 struct pipe_ctx *pipe_ctx; local
[all...] |
| amdgpu_dc_stream.c | 239 static void delay_cursor_until_vupdate(struct pipe_ctx *pipe_ctx, struct dc *dc)
244 struct dc_stream_state *stream = pipe_ctx->stream;
250 vupdate_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
278 struct pipe_ctx *pipe_to_program = NULL;
299 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; local
301 if (pipe_ctx->stream != stream)
305 pipe_to_program = pipe_ctx;
346 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; local
544 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; local
617 struct pipe_ctx *pipe_ctx = NULL; local
[all...] |
| amdgpu_dc.c | 126 * struct pipe_ctx - A member of struct resource_context. Represents the
292 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
319 struct pipe_ctx *pipe =
320 &dc->current_state->res_ctx.pipe_ctx[i];
348 struct pipe_ctx *pipe;
353 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
398 struct pipe_ctx *pipe;
402 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
423 struct pipe_ctx *pipe_ctx local
1486 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local
2054 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local
2205 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local
2224 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local
2289 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local
2307 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local
2331 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local
2414 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local
[all...] |
| amdgpu_dc_debug.c | 324 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; local
328 if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
331 pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);
336 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i] local
[all...] |
| amdgpu_dc_surface.c | 161 struct pipe_ctx *pipe_ctx = local
162 &dc->current_state->res_ctx.pipe_ctx[i];
164 if (pipe_ctx->plane_state != plane_state)
167 pipe_ctx->plane_state->status.is_flip_pending = false;
173 struct pipe_ctx *pipe_ctx = local
174 &dc->current_state->res_ctx.pipe_ctx[i];
176 if (pipe_ctx->plane_state != plane_state)
179 dc->hwss.update_pending_status(pipe_ctx);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dmub_psr.c | 107 struct pipe_ctx *pipe_ctx = NULL; local
112 res_ctx->pipe_ctx[i].stream &&
113 res_ctx->pipe_ctx[i].stream->link &&
114 res_ctx->pipe_ctx[i].stream->link == link &&
115 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
116 pipe_ctx = &res_ctx->pipe_ctx[i];
121 if (!pipe_ctx ||
122 !&pipe_ctx->plane_res |
[all...] |
