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    Searched refs:pll_post_divider (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
ppatomctrl.h 50 uint32_t pll_post_divider; member in struct:pp_atomctrl_clock_dividers
70 uint32_t pll_post_divider; member in struct:pp_atomctrl_clock_dividers_rv730
81 uint32_t pll_post_divider; member in struct:pp_atomctrl_clock_dividers_kong
87 uint32_t pll_post_divider; /* post divider value */ member in struct:pp_atomctrl_clock_dividers_ci
97 uint32_t pll_post_divider; /* post divider value */ member in struct:pp_atomctrl_clock_dividers_vi
amdgpu_smu8_hwmgr.c 494 (uint8_t)dividers.pll_post_divider;
511 (uint8_t)dividers.pll_post_divider;
525 (uint8_t)dividers.pll_post_divider;
537 (uint8_t)dividers.pll_post_divider;
551 (uint8_t)dividers.pll_post_divider;
amdgpu_ppatomctrl.c 368 dividers->pll_post_divider = pll_parameters.ucPostDiv;
392 dividers->pll_post_divider =
462 dividers->pll_post_divider =
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 938 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
1346 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1456 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1492 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1590 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1597 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
amdgpu_vegam_smumgr.c 1238 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1349 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1356 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
2114 PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
2117 PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
amdgpu_ci_smumgr.c 369 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
1414 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1546 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1553 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1586 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1616 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
amdgpu_tonga_smumgr.c 616 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
1211 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1353 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1362 (uint8_t)dividers.pll_post_divider;
1410 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1454 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
amdgpu_polaris10_smumgr.c 1333 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1437 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1444 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1998 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2000 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
amdgpu_iceland_smumgr.c 873 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
1462 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

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