| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/ |
| nouveau_nvkm_subdev_pmu_base.c | 37 struct nvkm_pmu *pmu = device->pmu; local in function:nvkm_pmu_fan_controlled
39 /* Internal PMU FW does not currently control fans in any way,
42 if (pmu && pmu->func->code.size)
45 /* Default (board-loaded, or VBIOS PMU/PREOS) PMU FW on Fermi
53 nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
55 if (pmu && pmu->func->pgob
62 struct nvkm_pmu *pmu = container_of(work, typeof(*pmu), recv.work); local in function:nvkm_pmu_recv
78 struct nvkm_pmu *pmu = nvkm_pmu(subdev); local in function:nvkm_pmu_intr
87 struct nvkm_pmu *pmu = nvkm_pmu(subdev); local in function:nvkm_pmu_fini
133 struct nvkm_pmu *pmu = nvkm_pmu(subdev); local in function:nvkm_pmu_preinit
140 struct nvkm_pmu *pmu = nvkm_pmu(subdev); local in function:nvkm_pmu_init
150 struct nvkm_pmu *pmu = nvkm_pmu(subdev); local in function:nvkm_pmu_dtor
212 struct nvkm_pmu *pmu; local in function:nvkm_pmu_new_
[all...] |
| nouveau_nvkm_subdev_pmu_gk20a.c | 56 gk20a_pmu_dvfs_target(struct gk20a_pmu *pmu, int *state)
58 struct nvkm_clk *clk = pmu->base.subdev.device->clk;
64 gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu *pmu, int *state)
66 struct nvkm_clk *clk = pmu->base.subdev.device->clk;
72 gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu,
75 struct gk20a_pmu_dvfs_data *data = pmu->data;
76 struct nvkm_clk *clk = pmu->base.subdev.device->clk;
91 nvkm_trace(&pmu->base.subdev, "cur level = %d, new level = %d\n",
100 gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu *pmu,
103 struct nvkm_falcon *falcon = &pmu->base.falcon
121 struct gk20a_pmu *pmu = local in function:gk20a_pmu_dvfs_work
220 struct gk20a_pmu *pmu; local in function:gk20a_pmu_new
[all...] |
| nouveau_nvkm_subdev_pmu_gp102.c | 32 gp102_pmu_reset(struct nvkm_pmu *pmu)
34 struct nvkm_device *device = pmu->subdev.device;
40 gp102_pmu_enabled(struct nvkm_pmu *pmu)
42 return !(nvkm_rd32(pmu->subdev.device, 0x10a3c0) & 0x00000001);
|
| nouveau_nvkm_subdev_pmu_gf100.c | 35 gf100_pmu_reset(struct nvkm_pmu *pmu)
37 struct nvkm_device *device = pmu->subdev.device;
43 gf100_pmu_enabled(struct nvkm_pmu *pmu)
45 return nvkm_mc_enabled(pmu->subdev.device, NVKM_SUBDEV_PMU);
65 gf100_pmu_nofw(struct nvkm_pmu *pmu, int ver, const struct nvkm_pmu_fwif *fwif)
|
| nouveau_nvkm_subdev_pmu_gt215.c | 35 gt215_pmu_send(struct nvkm_pmu *pmu, u32 reply[2],
38 struct nvkm_subdev *subdev = &pmu->subdev;
55 * on a synchronous reply, take the PMU mutex and tell the
59 pmu->recv.message = message;
60 pmu->recv.process = process;
70 pmu->send.base));
83 DRM_WAIT_NOINTR_UNTIL(ret, &pmu->recv.wait, &subdev->mutex,
84 (pmu->recv.process == 0));
86 reply[0] = pmu->recv.data[0];
87 reply[1] = pmu->recv.data[1]
[all...] |
| nouveau_nvkm_subdev_pmu_gm20b.c | 33 #include <nvfw/pmu.h>
47 struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon); local in function:gm20b_pmu_acr_bootstrap_falcon
57 ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
59 &pmu->subdev, msecs_to_jiffies(1000));
142 struct nvkm_pmu *pmu = priv; local in function:gm20b_pmu_acr_init_wpr_callback
143 struct nvkm_subdev *subdev = &pmu->subdev;
152 complete_all(&pmu->wpr_ready);
157 gm20b_pmu_acr_init_wpr(struct nvkm_pmu *pmu)
167 return nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr
[all...] |
| nouveau_nvkm_subdev_pmu_memx.c | 12 struct nvkm_pmu *pmu; member in struct:nvkm_memx
25 struct nvkm_device *device = memx->pmu->subdev.device;
49 nvkm_memx_init(struct nvkm_pmu *pmu, struct nvkm_memx **pmemx)
51 struct nvkm_device *device = pmu->subdev.device;
56 ret = nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
64 memx->pmu = pmu;
80 struct nvkm_pmu *pmu = memx->pmu; local in function:nvkm_memx_fini
81 struct nvkm_subdev *subdev = &pmu->subdev
[all...] |
| nouveau_nvkm_subdev_pmu_gp10b.c | 32 #include <nvfw/pmu.h>
45 struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon); local in function:gp10b_pmu_acr_bootstrap_multiple_falcons
57 ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
59 &pmu->subdev, msecs_to_jiffies(1000));
91 MODULE_FIRMWARE("nvidia/gp10b/pmu/desc.bin");
92 MODULE_FIRMWARE("nvidia/gp10b/pmu/image.bin");
93 MODULE_FIRMWARE("nvidia/gp10b/pmu/sig.bin");
|
| priv.h | 7 #include <subdev/pmu.h>
8 #include <subdev/pmu/fuc/os.h>
|
| nouveau_nvkm_subdev_pmu_gk104.c | 62 gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
64 struct nvkm_device *device = pmu->subdev.device;
|
| nouveau_nvkm_subdev_pmu_gk110.c | 37 gk110_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
39 struct nvkm_device *device = pmu->subdev.device;
|
| /src/sys/external/bsd/drm2/include/linux/ |
| perf_event.h | 37 struct pmu { struct
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_pmu.c | 87 static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
89 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
97 enable = pmu->enable;
155 struct i915_pmu *pmu = &i915->pmu; local in function:get_rc6
166 spin_lock_irqsave(&pmu->lock, flags);
169 pmu->sample[__I915_SAMPLE_RC6].cur = val;
178 val = ktime_since(pmu->sleep_last);
179 val += pmu->sample[__I915_SAMPLE_RC6].cur
194 struct i915_pmu *pmu = &i915->pmu; local in function:park_rc6
226 struct i915_pmu *pmu = &i915->pmu; local in function:i915_pmu_gt_parked
246 struct i915_pmu *pmu = &i915->pmu; local in function:i915_pmu_gt_unparked
291 struct intel_engine_pmu *pmu = &engine->pmu; local in function:engines_sample
360 struct i915_pmu *pmu = &i915->pmu; local in function:frequency_sample
405 struct i915_pmu *pmu = &i915->pmu; local in function:i915_sample
581 struct i915_pmu *pmu = &i915->pmu; local in function:__i915_pmu_event_read
644 struct i915_pmu *pmu = &i915->pmu; local in function:i915_pmu_enable
715 struct i915_pmu *pmu = &i915->pmu; local in function:i915_pmu_disable
1050 struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node); local in function:i915_pmu_cpu_online
1063 struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node); local in function:i915_pmu_cpu_offline
1125 struct i915_pmu *pmu = &i915->pmu; local in function:i915_pmu_register
1189 struct i915_pmu *pmu = &i915->pmu; local in function:i915_pmu_unregister
[all...] |
| i915_pmu.h | 28 * How many different events we track in the global PMU mask.
48 * @base: PMU base.
50 struct pmu base;
60 * @timer: Timer for internal i915 PMU sampling.
89 * are using the PMU API.
99 * These counters are updated from the i915 PMU sampling timer.
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/ |
| nouveau_nvkm_subdev_devinit_gm200.c | 33 #include <subdev/bios/pmu.h>
37 pmu_code(struct nv50_devinit *init, u32 pmu, u32 img, u32 len, bool sec)
43 nvkm_wr32(device, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu);
46 nvkm_wr32(device, 0x10a188, (pmu + i) >> 8);
57 pmu_data(struct nv50_devinit *init, u32 pmu, u32 img, u32 len)
63 nvkm_wr32(device, 0x10a1c0, 0x01000000 | pmu);
92 struct nvbios_pmuR pmu; local in function:pmu_load
94 if (!nvbios_pmuRm(bios, type, &pmu))
100 pmu_code(init, pmu.boot_addr_pmu, pmu.boot_addr, pmu.boot_size, false)
148 u32 pmu = pmu_args(init, args + 0x08, 0x08); local in function:gm200_devinit_post
156 u32 pmu = pmu_args(init, args + 0x08, 0x10); local in function:gm200_devinit_post
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_pmu.c | 39 /* record to keep track of pmu entry per pmu type per device */
43 struct pmu pmu; member in struct:amdgpu_pmu_entry
55 /* test the event attr type check for PMU enumeration */
56 if (event->attr.type != event->pmu->type)
69 struct amdgpu_pmu_entry *pe = container_of(event->pmu,
71 pmu);
98 struct amdgpu_pmu_entry *pe = container_of(event->pmu,
100 pmu);
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
| imx8-ss-ddr.dtsi | 13 ddr-pmu@5c020000 {
14 compatible = "fsl,imx8-ddr-pmu";
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| bcm28155-ap.dts | 52 pmu: pmu@8 { label
90 &pmu {
|
| arm-realview-eb-a9mp.dts | 68 &pmu {
|
| vf500.dtsi | 47 pmu@40089000 {
48 compatible = "arm,cortex-a5-pmu";
|
| arm-realview-eb-11mp.dts | 72 &pmu {
|
| bcm59056.dtsi | 7 &pmu {
|
| arm-realview-pba8.dts | 43 pmu: pmu@0 { label
44 compatible = "arm,cortex-a8-pmu";
|
| /src/sys/external/mit/xen-include-public/dist/xen/include/public/ |
| pmu.h | 28 #include "arch-x86/pmu.h"
42 * @cmd == XENPMU_* (PMU operation)
46 #define XENPMU_mode_get 0 /* Also used for getting PMU version */
72 /* PMU modes:
73 * - XENPMU_MODE_OFF: No PMU virtualization
86 * PMU features:
102 * Shared PMU data between hypervisor and PV(H) domains.
104 * The hypervisor fills out this structure during PMU interrupt and sends an
108 * by both the hypervisor and the guest (see arch-$arch/pmu.h).
130 struct xen_pmu_arch pmu; member in struct:xen_pmu_data
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/acr/ |
| nouveau_nvkm_subdev_acr_gm20b.c | 32 #include <subdev/pmu.h>
82 return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->pmu->falcon);
|
