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    Searched refs:postdiv (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/arch/arm/nxp/
imx_ccm_composite.c 133 for (u_int postdiv = 1; postdiv <= __SHIFTOUT_MASK(TARGET_ROOT_POST_PODF) + 1; postdiv++) { local in function:imx_ccm_composite_set_rate
134 const u_int cur_rate = prate / prediv / postdiv;
140 best_postdiv = postdiv;
146 best_postdiv = postdiv;
  /src/sys/arch/arm/ti/
ti_dpll_clock.c 344 const u_int postdiv = __SHIFTOUT(val, OMAP3_CORE_DPLL_CLKOUT_DIV); local in function:omap3_dpll_core_clock_get_rate
348 return (u_int)((mult * parent_rate) / div) / postdiv;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_vegam_smumgr.c 685 table->SclkFcwRangeTable[i].postdiv =
704 (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
706 (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
709 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
762 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
764 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
772 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
781 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
783 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
    [all...]
amdgpu_polaris10_smumgr.c 816 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
830 smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
831 smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
834 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
886 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
887 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
894 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
901 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
902 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu74_discrete.h 47 uint8_t postdiv; member in struct:sclkFcwRange_t
smu75_discrete.h 46 uint8_t postdiv; /* divide by 2^n */ member in struct:sclkFcwRange_t
162 uint8_t Postdiv;
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv770_dpm.c 347 static int rv770_encode_yclk_post_div(u32 postdiv, u32 *encoded_postdiv)
351 switch (postdiv) {

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