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  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
process_pptables_v1_0.h 33 struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *,
vega10_processpptables.h 62 struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *,
amdgpu_vega12_processpptables.c 362 uint32_t entry_index, struct pp_power_state *power_state,
374 power_state->classification.bios_index = entry_index;
394 result = call_back_func(hwmgr, (void *)state_entry, power_state,
401 if (!result && (power_state->classification.flags &
403 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
amdgpu_process_pptables_v1_0.c 1288 * @param power_state The address of the PowerState instance being created.
1292 uint32_t entry_index, struct pp_power_state *power_state,
1304 power_state->classification.bios_index = entry_index;
1322 result = call_back_func(hwmgr, __UNCONST(state_entry), power_state,
1329 if (!result && (power_state->classification.flags &
1331 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
amdgpu_vega10_processpptables.c 1335 uint32_t entry_index, struct pp_power_state *power_state,
1347 power_state->classification.bios_index = entry_index;
1367 result = call_back_func(hwmgr, __UNCONST(state_entry), power_state,
1374 if (!result && (power_state->classification.flags &
1376 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
amdgpu_smu7_hwmgr.c 3126 void *state, struct pp_power_state *power_state,
3131 (struct smu7_power_state *)(&(power_state->hardware));
3147 power_state->classification.ui_label =
3151 power_state->classification.flags = classification_flag;
3154 power_state->classification.temporary_state = false;
3155 power_state->classification.to_be_deleted = false;
3157 power_state->validation.disallowOnDC =
3161 power_state->pcie.lanes = 0;
3163 power_state->display.disableFrameModulation = false;
3164 power_state->display.limitRefreshrate = false
    [all...]
amdgpu_vega10_hwmgr.c 3030 void *state, struct pp_power_state *power_state,
3035 cast_phw_vega10_power_state(&(power_state->hardware));
3057 power_state->classification.ui_label =
3061 power_state->classification.flags = classification_flag;
3065 power_state->classification.temporary_state = false;
3066 power_state->classification.to_be_deleted = false;
3068 power_state->validation.disallowOnDC =
3072 power_state->display.disableFrameModulation = false;
3073 power_state->display.limitRefreshrate = false;
3074 power_state->display.enableVariBright
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
atombios_dp.h 40 u8 power_state);
amdgpu_atombios_dp.c 462 u8 power_state)
475 DP_SET_POWER, power_state);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_atombios.c 2052 rdev->pm.power_state[state_index].misc = misc;
2053 rdev->pm.power_state[state_index].misc2 = misc2;
2056 rdev->pm.power_state[state_index].type =
2059 rdev->pm.power_state[state_index].type =
2062 rdev->pm.power_state[state_index].type =
2065 rdev->pm.power_state[state_index].type =
2068 rdev->pm.power_state[state_index].type =
2070 rdev->pm.power_state[state_index].flags &=
2074 rdev->pm.power_state[state_index].type =
2077 rdev->pm.power_state[state_index].type
2573 union pplib_power_state *power_state; local in function:radeon_atombios_parse_power_table_4_5
2663 union pplib_power_state *power_state; local in function:radeon_atombios_parse_power_table_6
    [all...]
radeon_combios.c 2654 rdev->pm.power_state = kcalloc(2, sizeof(struct radeon_power_state),
2656 if (rdev->pm.power_state) {
2658 rdev->pm.power_state[0].clock_info =
2661 rdev->pm.power_state[1].clock_info =
2664 if (!rdev->pm.power_state[0].clock_info ||
2665 !rdev->pm.power_state[1].clock_info)
2741 rdev->pm.power_state[state_index].num_clock_modes = 1;
2742 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2743 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2744 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) |
    [all...]
radeon_pm.c 69 if (rdev->pm.power_state[i].type == ps_type) {
199 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
213 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
216 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
341 struct radeon_power_state *power_state; local in function:radeon_pm_print_states
346 power_state = &rdev->pm.power_state[i];
348 radeon_pm_state_type_name[power_state->type]);
352 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
353 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
    [all...]
radeon_rs780_dpm.c 799 union pplib_power_state *power_state; local in function:rs780_parse_power_table
820 power_state = (union pplib_power_state *)
827 (power_state->v1.ucNonClockStateIndex *
833 (power_state->v1.ucClockStateIndices[0] *
radeon_sumo_dpm.c 1461 union pplib_power_state *power_state; local in function:sumo_parse_power_table
1497 power_state = (union pplib_power_state *)power_state_offset;
1498 non_clock_array_index = power_state->v2.nonClockInfoIndex;
1501 if (!rdev->pm.power_state[i].clock_info)
1510 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
1511 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
1527 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
radeon_trinity_dpm.c 1738 union pplib_power_state *power_state; local in function:trinity_parse_power_table
1774 power_state = (union pplib_power_state *)power_state_offset;
1775 non_clock_array_index = power_state->v2.nonClockInfoIndex;
1778 if (!rdev->pm.power_state[i].clock_info)
1787 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
1788 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
1805 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
radeon_r600.c 396 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
419 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
432 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
467 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
469 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
470 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
500 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
509 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
517 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
534 rdev->pm.power_state[rdev->pm.requested_power_state_index]
    [all...]
radeon_atombios_dp.c 530 u8 power_state)
543 DP_SET_POWER, power_state);
radeon_r100.c 236 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
252 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
264 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
292 rdev->pm.power_state[rdev->pm.requested_power_state_index].
294 rdev->pm.power_state[rdev->pm.requested_power_state_index].
296 rdev->pm.power_state[rdev->pm.requested_power_state_index].
359 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
440 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
radeon_rs600.c 230 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
314 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
  /src/sys/dev/hpc/
hpcapm.c 82 volatile int power_state; member in struct:apmhpc_softc
124 sc->power_state = APM_SYS_READY;
179 if (sc->power_state != APM_SYS_STANDBY) {
186 if (sc->power_state != APM_SYS_SUSPEND) {
318 sc->power_state = APM_SYS_READY;
326 sc->power_state = APM_SYS_STANDBY;
340 sc->power_state = APM_SYS_SUSPEND;
350 sc->power_state = APM_SYS_OFF;
415 sc->power_state = APM_SYS_READY;
  /src/sys/arch/arm/arm/
psci.c 107 psci_cpu_suspend(uint32_t power_state)
109 return psci_call(psci_functions[PSCI_FUNC_CPU_SUSPEND], power_state,
  /src/sys/arch/zaurus/dev/
zapm.c 71 volatile int power_state; member in struct:zapm_softc
170 sc->power_state = APM_SYS_READY;
225 if (sc->power_state != APM_SYS_STANDBY) {
232 if (sc->power_state != APM_SYS_SUSPEND) {
368 sc->power_state = APM_SYS_READY;
382 sc->power_state = APM_SYS_OFF;
452 sc->power_state = APM_SYS_READY;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu_v11_0.h 132 enum smu_11_0_power_state power_state; member in struct:smu_11_0_power_context
  /src/sys/dev/acpi/
qcompas.c 1341 uint32_t power_state; member in struct:battmgr_bat_status
1579 if ((bat->power_state & BATTMGR_PWR_STATE_AC_ON) !=
1582 (bat->power_state & BATTMGR_PWR_STATE_AC_ON) != 0 ?
1586 (bat->power_state & BATTMGR_PWR_STATE_AC_ON) == 0 ?
1590 sc->sc_power_state = bat->power_state;
1592 (bat->power_state & BATTMGR_PWR_STATE_AC_ON) != 0;
  /src/sys/external/bsd/drm2/dist/drm/nouveau/
nouveau_acpi.c 223 .power_state = nouveau_dsm_power_state,

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