HomeSort by: relevance | last modified time | path
    Searched refs:pptable (Results 1 - 20 of 20) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_vega20_processpptables.c 72 static void dump_pptable(PPTable_t *pptable)
76 pr_info("Version = 0x%08x\n", pptable->Version);
78 pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
79 pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
81 pr_info("SocketPowerLimitAc0 = %d\n", pptable->SocketPowerLimitAc0);
82 pr_info("SocketPowerLimitAc0Tau = %d\n", pptable->SocketPowerLimitAc0Tau);
83 pr_info("SocketPowerLimitAc1 = %d\n", pptable->SocketPowerLimitAc1);
84 pr_info("SocketPowerLimitAc1Tau = %d\n", pptable->SocketPowerLimitAc1Tau);
85 pr_info("SocketPowerLimitAc2 = %d\n", pptable->SocketPowerLimitAc2);
86 pr_info("SocketPowerLimitAc2Tau = %d\n", pptable->SocketPowerLimitAc2Tau)
    [all...]
amdgpu_process_pptables_v1_0.c 214 (struct phm_ppt_v1_information *)(hwmgr->pptable);
257 struct phm_ppt_v1_information *pp_table_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
505 (struct phm_ppt_v1_information *)(hwmgr->pptable);
743 (struct phm_ppt_v1_information *)(hwmgr->pptable);
775 (struct phm_ppt_v1_information *)(hwmgr->pptable);
975 = (le32_to_cpu(tonga_fan_table->ulMinFanSCLKAcousticLimit) / 100); /* PPTable stores it in 10Khz unit for 2 decimal places. SMC wants MHz. */
1010 = (le32_to_cpu(fiji_fan_table->ulMinFanSCLKAcousticLimit) / 100); /* PPTable stores it in 10Khz unit for 2 decimal places. SMC wants MHz. */
1054 "Unsupported PPTable format!", return -1);
1070 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v1_information), GFP_KERNEL);
1072 PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),
1237 const ATOM_Tonga_POWERPLAYTABLE *pptable = get_powerplay_table(hwmgr); local in function:ppt_get_vce_state_table_entry_v1_0
    [all...]
amdgpu_vega12_processpptables.c 75 "Unsupported PPTable format!", return -1);
201 (struct phm_ppt_v3_information *)hwmgr->pptable;
276 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL);
277 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
278 "Failed to allocate hwmgr->pptable!", return -ENOMEM);
303 (struct phm_ppt_v3_information *)(hwmgr->pptable);
320 kfree(hwmgr->pptable);
321 hwmgr->pptable = NULL;
amdgpu_vega10_hwmgr.c 202 (struct phm_ppt_v2_information *)hwmgr->pptable;
312 (struct phm_ppt_v2_information *)(hwmgr->pptable);
529 (struct phm_ppt_v2_information *)(hwmgr->pptable);
566 (struct phm_ppt_v2_information *)hwmgr->pptable;
671 (struct phm_ppt_v2_information *)(hwmgr->pptable);
747 (struct phm_ppt_v2_information *)(hwmgr->pptable);
776 (struct phm_ppt_v2_information *)(hwmgr->pptable);
906 /* Parse pptable data read from VBIOS */
1168 (struct phm_ppt_v2_information *)hwmgr->pptable;
1257 (struct phm_ppt_v2_information *)(hwmgr->pptable);
    [all...]
amdgpu_vega10_processpptables.c 83 "Unsupported PPTable format!", return -1);
818 (struct phm_ppt_v2_information *)(hwmgr->pptable);
913 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1105 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1192 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL);
1194 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
1195 "Failed to allocate hwmgr->pptable!", return -ENOMEM);
1239 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1277 kfree(hwmgr->pptable);
1278 hwmgr->pptable = NULL
    [all...]
amdgpu_smu7_hwmgr.c 263 (struct phm_ppt_v1_information *)hwmgr->pptable;
540 (struct phm_ppt_v1_information *)(hwmgr->pptable);
570 * If PCIE table from PPTable have ULV entry + 8 entries,
767 (struct phm_ppt_v1_information *)(hwmgr->pptable);
833 (struct phm_ppt_v1_information *)(hwmgr->pptable);
878 (struct phm_ppt_v1_information *)(hwmgr->pptable);
906 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1562 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1711 (struct phm_ppt_v1_information *)hwmgr->pptable;
1844 (struct phm_ppt_v1_information *)(hwmgr->pptable);
    [all...]
amdgpu_smu_helper.c 471 (struct phm_ppt_v1_information *)(hwmgr->pptable);
501 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
541 (struct phm_ppt_v1_information *)hwmgr->pptable;
amdgpu_vega20_hwmgr.c 462 /* Parse pptable data read from VBIOS */
800 (struct phm_ppt_v3_information *)hwmgr->pptable;
829 "[InitSMCTable] Failed to upload PPtable!",
836 * Override PCIe link speed and link width for DPM Level 1. PPTable entries
1023 (struct phm_ppt_v3_information *)hwmgr->pptable;
1223 (struct phm_ppt_v3_information *)hwmgr->pptable;
2753 (struct phm_ppt_v2_information *)hwmgr->pptable;
3269 (struct phm_ppt_v3_information *)hwmgr->pptable;
3270 PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable; local in function:vega20_print_clock_levels
3376 gen_speed = pptable->PcieGenSpeed[i]
    [all...]
amdgpu_smu10_hwmgr.c 417 struct smu10_voltage_dependency_table **pptable,
437 *pptable = ptable;
amdgpu_vega10_powertune.c 1294 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1344 (struct phm_ppt_v2_information *)(hwmgr->pptable);
amdgpu_smu7_powertune.c 1118 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1203 (struct phm_ppt_v1_information *)(hwmgr->pptable);
amdgpu_vega12_hwmgr.c 417 /* Parse pptable data read from VBIOS */
742 (struct phm_ppt_v3_information *)hwmgr->pptable;
767 "Failed to upload PPtable!", return result);
1690 (struct phm_ppt_v2_information *)hwmgr->pptable;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_arcturus_ppt.c 178 TAB_MAP(PPTABLE),
365 /* pptable will handle the features to enable */
859 PPTable_t *pptable = smu->smu_table.driver_pptable; local in function:arcturus_get_thermal_temperature_range
864 range->max = pptable->TedgeLimit *
866 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
868 range->hotspot_crit_max = pptable->ThotspotLimit *
870 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
872 range->mem_crit_max = pptable->TmemLimit *
874 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
991 PPTable_t *pptable = table_context->driver_pptable local in function:arcturus_read_sensor
1050 PPTable_t *pptable = smu->smu_table.driver_pptable; local in function:arcturus_get_fan_speed_percent
1290 PPTable_t *pptable = smu->smu_table.driver_pptable; local in function:arcturus_get_power_limit
1529 PPTable_t *pptable = table_context->driver_pptable; local in function:arcturus_dump_pptable
2231 PPTable_t *pptable = smu->smu_table.driver_pptable; local in function:arcturus_get_pptable_power_limit
    [all...]
amdgpu_navi10_ppt.c 199 TAB_MAP(PPTABLE),
737 PPTable_t *pptable = smu->smu_table.driver_pptable; local in function:navi10_is_support_fine_grained_dpm
742 dpm_desc = &pptable->DpmDescriptor[clk_index];
776 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; local in function:navi10_print_clk_levels
850 pptable->LclkFreq[i],
1229 PPTable_t *pptable = smu->smu_table.driver_pptable; local in function:navi10_get_fan_speed_percent
1235 percent = current_rpm * 100 / pptable->FanMaximumRpm;
1600 PPTable_t *pptable = table_context->driver_pptable; local in function:navi10_read_sensor
1608 *(uint32_t *)data = pptable->FanMaximumRpm;
1847 PPTable_t *pptable = smu->smu_table.driver_pptable local in function:navi10_get_pptable_power_limit
1855 PPTable_t *pptable = smu->smu_table.driver_pptable; local in function:navi10_get_power_limit
1898 PPTable_t *pptable = smu->smu_table.driver_pptable; local in function:navi10_update_pcie_parameters
    [all...]
amdgpu_vega20_ppt.c 208 TAB_MAP(PPTABLE),
583 pr_err("Unsupported PPTable format!");
966 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; local in function:vega20_print_clk_levels
1078 (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
1079 (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
1080 (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
1081 (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
1082 (pptable->PcieLaneCount[i] == 1) ? "x1" :
1083 (pptable->PcieLaneCount[i] == 2) ? "x2" :
1084 (pptable->PcieLaneCount[i] == 3) ? "x4"
2861 PPTable_t *pptable = table_context->driver_pptable; local in function:vega20_set_thermal_fan_table
2891 PPTable_t *pptable = smu->smu_table.driver_pptable; local in function:vega20_get_fan_speed_percent
3006 PPTable_t *pptable = table_context->driver_pptable; local in function:vega20_read_sensor
3107 PPTable_t *pptable = smu->smu_table.driver_pptable; local in function:vega20_get_thermal_temperature_range
3154 PPTable_t *pptable = smu->smu_table.driver_pptable; local in function:vega20_update_pcie_parameters
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_vegam_smumgr.c 341 (struct phm_ppt_v1_information *)(hwmgr->pptable);
373 (struct phm_ppt_v1_information *)(hwmgr->pptable);
404 (struct phm_ppt_v1_information *)(hwmgr->pptable);
439 (struct phm_ppt_v1_information *)(hwmgr->pptable);
511 (struct phm_ppt_v1_information *)(hwmgr->pptable);
548 (struct phm_ppt_v1_information *)(hwmgr->pptable);
819 (struct phm_ppt_v1_information *)(hwmgr->pptable);
872 (struct phm_ppt_v1_information *)(hwmgr->pptable);
921 "There must be 1 or more PCIE levels defined in PPTable.",
988 (struct phm_ppt_v1_information *)(hwmgr->pptable);
    [all...]
amdgpu_fiji_smumgr.c 478 (struct phm_ppt_v1_information *)(hwmgr->pptable);
500 (struct phm_ppt_v1_information *)(hwmgr->pptable);
594 (struct phm_ppt_v1_information *)(hwmgr->pptable);
680 (struct phm_ppt_v1_information *)(hwmgr->pptable);
768 (struct phm_ppt_v1_information *)(hwmgr->pptable);
808 (struct phm_ppt_v1_information *)(hwmgr->pptable);
951 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1013 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1055 "There must be 1 or more PCIE levels defined in PPTable.",
1173 (struct phm_ppt_v1_information *)(hwmgr->pptable);
    [all...]
amdgpu_polaris10_smumgr.c 436 (struct phm_ppt_v1_information *)(hwmgr->pptable);
495 (struct phm_ppt_v1_information *)(hwmgr->pptable);
575 (struct phm_ppt_v1_information *)(hwmgr->pptable);
710 (struct phm_ppt_v1_information *)(hwmgr->pptable);
744 (struct phm_ppt_v1_information *)(hwmgr->pptable);
919 (struct phm_ppt_v1_information *)(hwmgr->pptable);
988 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1031 "There must be 1 or more PCIE levels defined in PPTable.",
1081 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1184 (struct phm_ppt_v1_information *)(hwmgr->pptable);
    [all...]
amdgpu_tonga_smumgr.c 258 (struct phm_ppt_v1_information *)(hwmgr->pptable);
403 (struct phm_ppt_v1_information *)(hwmgr->pptable);
488 (struct phm_ppt_v1_information *)(hwmgr->pptable);
629 (struct phm_ppt_v1_information *)(hwmgr->pptable);
695 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
742 "There must be 1 or more PCIE levels defined in PPTable.",
972 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1153 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1321 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1381 (struct phm_ppt_v1_information *)(hwmgr->pptable);
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
hwmgr.h 526 /* Structure to hold PPTable information */
685 uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
764 void *pptable; member in struct:pp_hwmgr

Completed in 70 milliseconds