| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_psr.c | 42 * DOC: Panel Self Refresh (PSR/SRD)
45 * panels witch have a remote frame buffer (RFB) implemented according to PSR
46 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
54 * PSR saves power by caching the framebuffer in the panel RFB, which allows us
58 * The implementation uses the hardware-based PSR support which automatically
63 * part doesn't work too well, hence why the i915 PSR support uses the
90 switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
112 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
114 trans_shift = dev_priv->psr.transcoder;
119 if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ
1013 struct i915_psr *psr = &dev_priv->psr; local in function:intel_psr_update
1201 struct i915_psr *psr = &dev_priv->psr; local in function:intel_psr_handle_irq
1424 struct i915_psr *psr = &dev_priv->psr; local in function:psr_alpm_check
1450 struct i915_psr *psr = &dev_priv->psr; local in function:psr_capability_changed_check
1473 struct i915_psr *psr = &dev_priv->psr; local in function:intel_psr_short_pulse
[all...] |
| intel_bios.c | 683 dev_priv->vbt.psr.enable = driver->psr_enabled;
701 dev_priv->vbt.psr.enable = power->psr & BIT(panel_type);
827 const struct bdb_psr *psr; local in function:parse_psr
831 psr = find_section(bdb, BDB_PSR);
832 if (!psr) {
833 DRM_DEBUG_KMS("No PSR BDB found.\n");
837 psr_table = &psr->psr_table[panel_type];
839 dev_priv->vbt.psr.full_link = psr_table->full_link;
840 dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup
[all...] |
| /src/sys/arch/ia64/stand/ia64/ski/ |
| ssc.c | 39 * PSR.dt register is not preserved properly and causes further memory
41 * PSR.dt across the SSC call. We do this by saving and restoring psr.l
49 register u_int64_t psr; local in function:ssc
52 __asm __volatile("mov %0=psr;;" : "=r"(psr));
57 __asm __volatile("mov psr.l=%0;; srlz.d" :: "r"(psr));
|
| /src/sys/arch/ia64/stand/efi/libefi/ |
| exec.c | 99 u_int64_t psr; local in function:disable_ic
100 __asm __volatile("mov %0=psr;;" : "=r" (psr));
101 __asm __volatile("rsm psr.ic|psr.i;; srlz.i;;");
102 return psr;
106 restore_ic(u_int64_t psr)
108 __asm __volatile("mov psr.l=%0;; srlz.i" :: "r" (psr));
112 * Entered with psr.ic and psr.i both zero
117 u_int64_t psr; local in function:enter_kernel
138 u_int64_t psr; local in function:elf64_exec
[all...] |
| /src/sys/arch/sparc/include/ |
| psl.h | 91 * SPARC V9 PSTATE register (what replaces the PSR in V9)
243 * GCC pseudo-functions for manipulating PSR (primarily PIL field).
248 int psr; local in function:getpsr
250 __asm volatile("rd %%psr,%0" : "=r" (psr));
251 return (psr);
266 __asm volatile("wr %0,0,%%psr" : : "r" (newpsr) : "memory");
273 int psr, oldipl; local in function:spl0
276 * wrpsr xors two values: we choose old psr and old ipl here,
277 * which gives us the same value as the old psr but with al
321 int psr, oldipl; local in function:splraiseipl
352 int psr; local in function:splx
[all...] |
| /src/sys/external/bsd/gnu-efi/dist/lib/ia64/ |
| palproc.S | 55 mov r2 = psr;;
69 (p7)dep r2 = loc6,r2,13,1;; // psr.ic = 1
72 // on psr.ic for these values. For now, do not do any thing to psr.ic
74 // (p6)dep r2 = r0,r2,13,1;; // psr.ic = 0
75 dep r2 = r0,r2,14,1;; // psr.i = 0
77 mov psr.l = r2
94 mov psr.l = loc5;;
135 mov r2 = psr;;
137 dep r2 = r0,r2,14,1;; // psr.i =
[all...] |
| /src/sys/arch/ia64/ia64/ |
| trap.c | 227 printpsr(uint64_t psr)
229 printbits(psr, psr_bits, sizeof(psr_bits)/sizeof(psr_bits[0]));
264 printf(" cr.ipsr = 0x%lx (", tf->tf_special.psr);
265 printpsr(tf->tf_special.psr);
271 if (tf->tf_special.psr & IA64_PSR_IS) {
301 slot = ((tf->tf_special.psr & IA64_PSR_RI) == IA64_PSR_RI_0) ? 0 :
302 ((tf->tf_special.psr & IA64_PSR_RI) == IA64_PSR_RI_1) ? 1 : 2;
520 tf->tf_special.psr &= ~IA64_PSR_SS;
592 tf->tf_special.psr &= ~IA64_PSR_RI;
615 tf->tf_special.psr &= ~IA64_PSR_RI
[all...] |
| pal.S | 59 mov psrsave=psr
71 rsm psr.i // disable interrupts
74 2: mov psr.l=psrsave
155 mov psrsave=psr
166 rsm psr.i // disable interrupts
169 mov psr.l=psrsave
|
| db_interface.c | 165 slot = (f->tf_special.psr >> 41) & 3;
175 f->tf_special.psr &= ~IA64_PSR_RI;
176 f->tf_special.psr |= slot << 41;
233 {"psr", DB_OFFSET(tf_special.psr), db_frame},
428 regs->tf_special.psr += IA64_PSR_RI_1;
429 if ((regs->tf_special.psr & IA64_PSR_RI) > IA64_PSR_RI_2) {
430 regs->tf_special.psr &= ~IA64_PSR_RI;
|
| machdep.c | 268 uint64_t psr; local in function:map_vhpt
283 __asm __volatile("mov %0=psr" : "=r"(psr));
284 __asm __volatile("rsm psr.ic|psr.i");
290 __asm __volatile("mov psr.l=%0" :: "r" (psr));
298 uint64_t psr; local in function:map_pal_code
311 __asm __volatile("mov %0=psr" : "=r"(psr));
330 uint64_t psr; local in function:map_gateway_page
[all...] |
| exception.S | 305 rsm psr.dt
374 st8 [r31]=r23,16 // psr
547 ssm psr.dt|psr.ic|psr.dfh
567 rsm psr.i
576 rsm psr.dt|psr.ic
719 ld8 r24=[r31],16 // psr
754 ssm psr.d
[all...] |
| syscall_stubs.S | 50 * also make sure we have a reliable psr.
66 * r11 - copy of psr.l
92 mov r11=psr
97 rum psr.be
313 dep r11=-1,r11,44,1 // Set psr.bn=1
319 dep r11=-1,r11,32,2 // Set psr.cpl=3
324 st8 [r31]=r11,16 // psr
385 ssm psr.dfh|psr.ac
460 ld8 r26=[r14],16 // psr
[all...] |
| /src/sys/arch/sparc/sparc/ |
| lock_stubs.s | 130 rd %psr, %o1
137 wr %o2, %o1, %psr
177 rd %psr, %o1
179 wr %o3, %o1, %psr
200 rd %psr, %o4 ! disable interrupts
202 wr %o5, 0, %psr
225 wr %o4, 0, %psr ! enable interrupts
233 wr %o4, 0, %psr ! enable interrupts
|
| process_machdep.c | 125 int psr = l->l_md.md_tf->tf_psr & ~PSR_ICC; local in function:process_write_regs
131 l->l_md.md_tf->tf_psr = psr | (regs->r_psr & PSR_ICC);
|
| locore.s | 267 * %l2 respectively. We use two more to read the psr into %l0, and to
297 mov (type), %l3; b label; mov %psr, %l0; nop
301 mov (lev), %l3; b _C_LABEL(sparc_interrupt44c); mov %psr, %l0; nop
305 mov (lev), %l3; b _C_LABEL(sparc_interrupt4m); mov %psr, %l0; nop
310 mov (lev), %l3; mov (bit), %l4; b softintr_sun44c; mov %psr, %l0
333 #define SYSCALL b _C_LABEL(_syscall); mov %psr, %l0; nop; nop
334 #define WINDOW_OF b window_of; mov %psr, %l0; nop; nop
335 #define WINDOW_UF b window_uf; mov %psr, %l0; nop; nop
337 #define ZS_INTERRUPT b zshard; mov %psr, %l0; nop; nop
368 TRAP(T_FPDISABLED) ! 04 = fp instr, but EF bit off in psr
[all...] |
| trap.c | 222 trap(unsigned type, int psr, int pc, struct trapframe *tf)
241 if (psr & PSR_PS) {
297 snprintb(bits, sizeof(bits), PSR_BITS, psr);
298 printf("trap type 0x%x: pc=0x%x npc=0x%x psr=%s\n",
335 snprintb(bits, sizeof(bits), PSR_BITS, psr);
336 printf("trap type 0x%x: pc=0x%x npc=0x%x psr=%s\n",
759 mem_access_fault(unsigned type, int ser, u_int v, int pc, int psr,
826 if (psr & PSR_PS) {
922 if (psr & PSR_PS) {
965 if ((psr & PSR_PS) == 0)
978 int pc, psr; local in function:mem_access_fault4m
[all...] |
| /src/sys/external/bsd/gnu-efi/dist/gnuefi/ |
| crt0-efi-ia64.S | 38 .psr abi64
39 .psr lsb
|
| /src/sys/arch/sparc/stand/common/ |
| srt0.S | 94 wr %g0, 0, %wim ! make sure we can set psr
96 wr %g0, PSR_S|PSR_PS|PSR_PIL, %psr ! set initial psr
100 rd %psr, %l0
101 wr %l0, PSR_ET, %psr
134 rd %psr, %o0
136 wr %o0, 0xb00, %psr ! (11 << 8)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dmub_psr.c | 42 * Get PSR state from firmware.
51 * Enable/Disable PSR.
73 * Set PSR level.
97 * Setup PSR by programming phy registers and sending psr hw context values to firmware.
193 * Construct PSR object.
195 static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)
197 psr->ctx = ctx;
198 psr->funcs = &psr_funcs;
202 * Allocate and initialize PSR object
206 struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL); local in function:dmub_psr_create
[all...] |
| /src/common/lib/libc/arch/sparc/atomic/ |
| atomic_cas.S | 42 rd %psr, %o4 /* disable interrupts */;\
44 wr %o5, 0, %psr ;\
50 wr %o4, 0, %psr /* enable interrupts */ ;\
74 /* o4 is not used for PSR in PIC cases, so we can use it here */
130 ! %o4 has saved PSR value
|
| /src/sys/arch/ia64/include/ |
| db_machdep.h | 56 ((db_addr_t)(regs)->tf_special.iip + (((regs)->tf_special.psr>>41) & 3))
60 #define PC_REGS(regs) ((db_addr_t)(regs)->tf_special.iip + (((regs)->tf_special.psr>>41) & 3))
63 #define db_set_single_step(regs) ((regs)->tf_special.psr |= IA64_PSR_SS)
64 #define db_clear_single_step(regs) ((regs)->tf_special.psr &= ~IA64_PSR_SS)
|
| cpufunc.h | 201 __asm __volatile ("rsm psr.i");
208 __asm __volatile ("ssm psr.i;; srlz.d");
214 register_t psr; local in function:intr_disable
216 __asm __volatile ("mov %0=psr;;" : "=r"(psr));
218 return (psr & IA64_PSR_I) ? 1 : 0;
|
| cpu.h | 153 #define TRAPF_CPL(tf) ((tf)->tf_special.psr & IA64_PSR_CPL)
|
| /src/sys/arch/arm/include/ |
| locore.h | 127 * Validate a PC or PSR for a user process. Used by various system calls
132 #define VALID_PSR(psr) \
133 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & I32_bit) == 0)
135 #define VALID_PSR(psr) \
136 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & IF32_bits) == 0)
|
| /src/sys/arch/evbppc/obs405/ |
| obs200_machdep.c | 124 u_int32_t psr __debugused;
131 psr = mfdcr(DCR_CPC0_PSR);
152 printf(" Chip Pin Strapping Register = 0x%08x\n", psr);
|
