| /src/lib/libc/arch/arm/gen/ |
| alloca.S | 40 adds r0, r0, #7 /* round up to next 8 byte alignment */
42 bics r0, r0, #7
43 sub sp, sp, r0 /* Adjust the stack pointer */
44 mov r0, sp /* r0 = base of new space */
46 lsrs r0, r0, #3
47 lsls r0, r0, #
[all...] |
| /src/common/lib/libc/arch/arm/string/ |
| ffs.S | 57 neg r1, r0
58 and r0, r0, r1
59 clz r0, r0
60 rsb r0, r0, #32
65 /* Standard trick to isolate bottom bit in r0 or 0 if r0 = 0 on entry */
66 neg r1, r0
[all...] |
| strlen_naive.S | 36 adds r3, r0, #1 /* start of src + NUL */
38 adds r2, r0, r1 /* &src[maxlen] */
41 adds ip, r0, r1 /* &src[maxlen] */
43 1: cmp r0, ip /* is this the end of string? */
46 ldrb r2, [r0] /* read a byte */
47 adds r0, r0, #1 /* advance to next byte */
49 ldrb r2, [r0], #1 /* read a byte */
53 subs r0, r0, r3 /* get difference between start and end *
[all...] |
| strcat_naive.S | 35 mov ip, r0 /* need to preserve r0 */
37 1: ldrb r2, [r0] /* load next byte */
38 adds r0, r0, #1 /* advance */
41 subs r0, r0, #1 /* back up one to the NUL */
42 subs r1, r1, r0 /* save one increment */
43 2: ldrb r2, [r1, r0] /* load next byte from append */
44 strb r2, [r0] /* store it *
[all...] |
| strncmp.S | 41 movmi r0, #0
47 adds r3, r0, r2
49 subs r1, r1, r0
51 add ip, r0, r2
55 ldrb r2, [r0]
56 ldrb r3, [r1, r0]
57 adds r0, r0, #1
58 cmp ip, r0 /* exhausted length? */
64 ldrb r2, [r0], #
[all...] |
| /src/sys/arch/powerpc/booke/ |
| spe_subr.S | 46 * r0's high half since we are about to load it.
48 evldd %r0,(8 << 4)(%r3)
49 evmra %r0,%r0
63 * The evmergelo will move the lower half of r0 to the high half of the
64 * destination register and evmergehilo will merge the high half of r0
67 evldw %r0,(30 << 2)(%r3)
68 evmergelo %r31,%r0,%r31; evmergehilo %r30,%r0,%r30
69 evldw %r0,(28 << 2)(%r3
[all...] |
| /src/common/lib/libc/arch/arm/gen/ |
| byte_swap_4.S | 41 rev r0, r0
43 eor r1, r0, r0, ror #16 /* d.c.b.a -> db.ca.db.ca */
45 mov r0, r0, ror #8 /* d.c.b.a -> a.d.c.b */
46 eor r0, r0, r1, lsr #8 /* a.d.c.b ^ 0.db.0.db -> a.b.c.d */
49 lsls r1, r0, #8 /* d.c.b.a -> c.b.a.0 */
50 lsrs r0, r0, #8 /* d.c.b.a -> 0.d.c.b *
[all...] |
| byte_swap_2.S | 42 rev16 r0, r0
44 and r1, r0, #0xff
45 mov r0, r0, lsr #8
46 orr r0, r0, r1, lsl #8
49 movs r1, r0
52 lsrs r0, r0, #
[all...] |
| neon_mask.S | 38 * IN r0 = length of mask in bits
42 cmp r0, #64 /* which dword is partial? */
44 sublt r0, r0, #64 /* 1st dword needs MSBs cleared */
45 subge r1, r0, #128 /* 2nd dword needs MSBs cleared */
47 rsblt r0, r0, #64 /* 1st dword needs LSBs cleared */
48 rsbge r1, r0, #128 /* 2nd dword needs LSBs cleared */
50 movge r0, #0 /* 1st dword needs to left alone */
52 vmov d2, r0, r1 /* move dword shifts to SIMD *
[all...] |
| /src/sys/external/bsd/compiler_rt/dist/lib/builtins/arm/ |
| clzdi2.S | 31 cmp r0, 0
33 clzne r0, r0
34 clzeq r0, r1
35 addeq r0, r0, 32
39 clzne r0, r1
40 clzeq r0, r0
41 addeq r0, r0, 3
[all...] |
| bswapdi2.S | 31 // r2 = rev(r0)
32 eor r2, r0, r0, ror #16
35 eor r2, r2, r0, ror #8
36 // r0 = rev(r1)
37 eor r0, r1, r1, ror #16
38 bic r0, r0, #0xff0000
39 mov r0, r0, lsr #
[all...] |
| switch16.S | 16 // case statement. On entry, R0 is the index into the table. The __switch*
19 // It then uses R0 to index into the table and get the displacement of the
20 // address to jump to. If R0 is greater than the size of the table, it jumps
35 cmp r0, ip // compare with index
36 add r0, lr, r0, lsl #1 // compute address of element in table
39 ldrshlo r0, [r0, #1] // load 16-bit element if r0 is in range
40 ldrshhs r0, [ip, #1] // load 16-bit element if r0 out of rang
[all...] |
| switch32.S | 16 // case statement. On entry, R0 is the index into the table. The __switch*
19 // It then uses R0 to index into the table and get the displacement of the
20 // address to jump to. If R0 is greater than the size of the table, it jumps
35 cmp r0, ip // compare with index
36 add r0, lr, r0, lsl #2 // compute address of element in table
39 ldrlo r0, [r0, #3] // load 32-bit element if r0 is in range
40 ldrhs r0, [ip, #3] // load 32-bit element if r0 out of rang
[all...] |
| /src/common/lib/libc/arch/sh3/string/ |
| ffs.S | 47 mov r4,r0 ! using r0 specific instructions
48 tst #0xff,r0
52 tst r0,r0 ! ffs(0) is 0
55 shlr8 r0
56 tst #0xff,r0
60 shlr8 r0
61 tst #0xff,r0
65 shlr8 r0
[all...] |
| /src/sys/arch/arm/arm/ |
| cpu_in_cksum_v4hdr.S | 36 tst r0, #4 /* 64-bit aligned? */
37 ldreqd r2, [r0], #8 /* load 1st/2nd words */
38 ldrne ip, [r0], #4 /* load 1st word */
39 ldreq ip, [r0, #8] /* load 5th word */
40 ldrned r2, [r0, #8] /* load 4th/5th words */
42 ldr ip, [r0] /* load 1st word */
43 ldr r3, [r0, #4] /* load 2nd word */
44 ldr r2, [r0, #8] /* load 3rd word */
49 ldrd r0, [r0] /* load remaining words *
[all...] |
| cpufunc_asm_arm11.S | 50 mcr p15, 0, r0, c2, c0, 0 /* set the new TTBR0 */
52 mcreq p15, 0, r0, c2, c0, 1 /* set the new TTBR1 */
54 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
55 mcrne p15, 0, r0, c7, c10, 4 /* drain write buffer */
71 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
72 mcr p15, 0, r0, c2, c0, 0 /* set the new TTBR0 */
75 mcreq p15, 0, r0, c2, c0, 1 /* set the new TTBR1 */
77 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
92 mov r0, #0
93 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb *
[all...] |
| cpufunc_asm_arm10.S | 42 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
43 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
45 add r0, r0, #L2_S_SIZE
46 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
47 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
53 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
55 add r0, r0, #L2_S_SIZE
56 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry *
[all...] |
| /src/sys/lib/libkern/arch/sh3/ |
| movstr.S | 38 mov #16, r0
39 cmp/gt r0, r6
44 mov.l @r5+, r0
45 mov.l r0, @r4
46 mov.l @r5+, r0
47 mov.l r0, @(4, r4)
48 mov.l @r5+, r0
49 mov.l r0, @(8, r4)
50 mov.l @r5+, r0
51 mov.l r0, @(12, r4
[all...] |
| /src/lib/libc/arch/sh3/sys/ |
| brk.S | 58 mova L_GOT, r0
60 add r0, r2
61 mov.l Lminbrk, r0
62 mov.l @(r0, r2), r0
63 mov.l @r0, r0
65 mov.l Lminbrk, r0
66 mov.l @r0, r0
[all...] |
| /src/lib/libc/arch/vax/gen/ |
| fabs.S | 42 movd 4(%ap),%r0
44 mnegd %r0,%r0
|
| fabsf.S | 40 movf 4(%ap),%r0
42 mnegf %r0,%r0
|
| /src/lib/libc/arch/vax/string/ |
| ffs.S | 41 ffs $0,$32,4(%ap),%r0
43 mnegl $1,%r0
45 incl %r0
|
| /src/lib/libc/compat/arch/arm/sys/ |
| compat_sigpending.S | 40 mov r2, r0
43 str r0, [r2]
44 movs r0, #0
|
| compat_sigsuspend.S | 40 ldr r0, [r0]
43 movs r0, #0
|
| /src/sys/arch/evbarm/ixm1200/ |
| ixm1200_start.S | 62 mrc p15, 0, r0, c1, c0 ,0 /* read ctrl */
63 bic r0, r0, #CPU_CONTROL_MMU_ENABLE
64 bic r0, r0, #CPU_CONTROL_AFLT_ENABLE
65 orr r0, r0, #CPU_CONTROL_DC_ENABLE
66 orr r0, r0, #CPU_CONTROL_WBUF_ENABLE
67 bic r0, r0, #CPU_CONTROL_BEND_ENABL
[all...] |
