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  /src/sys/arch/evbmips/loongson/dev/
glxvar.h 21 uint64_t rdmsr(uint);
glx.c 133 msr = rdmsr(GCSC_DIVIL_BALL_OPTS); /* 0x71 */
171 DPRINTF(("IO space 0x%" PRIx64 "\n", rdmsr(0x80000014)));
175 rdmsr(uint msr) function in typeref:typename:uint64_t
182 panic("rdmsr invoked before glx initialization");
316 msr = rdmsr(GCSC_GLPCI_GLD_MSR_ERROR);
372 msr = rdmsr(GCSC_DIVIL_LBAR_SMB);
377 msr = rdmsr(GCSC_GLCP_CHIP_REV_ID);
383 msr = rdmsr(GCSC_GLPCI_CTRL);
403 data = (pcireg_t)rdmsr(pcib_bar_msr[index]);
432 msr = rdmsr(pcib_bar_msr[index])
    [all...]
gcscpcib_pci.c 101 return rdmsr(msr);
  /src/share/man/man9/man9.x86/
Makefile 3 MAN= nmi.9 rdmsr.9 tsc.9 x86_msr_xcall.9
10 MLINKS+=rdmsr.9 msr.9 \
11 rdmsr.9 rdmsr_safe.9 \
12 rdmsr.9 wrmsr.9
  /src/sys/arch/x86/include/
cpu_msr.h 53 msr = rdmsr(msrdat->msr_type);
  /src/sys/arch/x86/x86/
intel_busclock.c 53 msr = rdmsr(MSR_EBL_CR_POWERON);
81 msr = rdmsr(MSR_PERF_STATUS);
189 msr = rdmsr(MSR_EBL_CR_POWERON);
323 aprint_debug(" (0x%" PRIu64 ")\n", rdmsr(MSR_EBL_CR_POWERON));
336 msr = rdmsr(MSR_EBC_FREQUENCY_ID);
hyperv.c 163 return (u_int)rdmsr(MSR_HV_TIME_REF_COUNT);
170 return rdmsr(MSR_HV_TIME_REF_COUNT);
227 /* Fallback to the generic timecounter, i.e. rdmsr. */
228 return rdmsr(MSR_HV_TIME_REF_COUNT);
265 orig_msr = rdmsr(MSR_HV_REFERENCE_TSC);
315 last = (u_int)rdmsr(MSR_HV_TIME_REF_COUNT);
318 u = (u_int)rdmsr(MSR_HV_TIME_REF_COUNT);
495 hyperv_vcpuid[0] = rdmsr(MSR_HV_VP_INDEX);
514 hyperv_vcpuid[ci->ci_index] = rdmsr(MSR_HV_VP_INDEX);
560 lapic_per_second = rdmsr(MSR_HV_APIC_FREQUENCY)
    [all...]
coretemp.c 171 msr = rdmsr(MSR_THERM_STATUS);
238 msr = rdmsr(MSR_THERM_STATUS);
252 msr = rdmsr(MSR_BIOS_SIGN);
365 msr = rdmsr(MSR_THERM_STATUS);
cpu_ucode_intel.c 60 msr = rdmsr(MSR_BIOS_SIGN);
65 msr = rdmsr(MSR_IA32_PLATFORM_ID);
spectre.c 131 msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
259 msr = rdmsr(MSR_IA32_SPEC_CTRL);
268 msr = rdmsr(MSR_IC_CFG);
413 msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
485 msr = rdmsr(msrval);
684 msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
802 msr = rdmsr(MSR_IA32_TSX_CTRL);
854 msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
cpu_ucode_amd.c 117 data->version = rdmsr(MSR_UCODE_AMD_PATCHLEVEL);
185 patchlevel = rdmsr(MSR_UCODE_AMD_PATCHLEVEL);
193 if (patchlevel == rdmsr(MSR_UCODE_AMD_PATCHLEVEL)) {
identcpu.c 171 rdmsr(MSR_MISC_ENABLE) & ~IA32_MISC_MWAIT_EN);
349 val = rdmsr(MSR_BU_CFG2);
514 wrmsr(MSR_VIA_FCR, rdmsr(MSR_VIA_FCR) | VIA_FCR_CX8_REPORT);
545 msr = rdmsr(MSR_VIA_FCR);
610 msr = rdmsr(MSR_VIA_RNG);
620 msr = rdmsr(MSR_VIA_FCR);
984 (rdmsr(MSR_MISC_ENABLE) & (1 << 3)) == 0) {
986 wrmsr(MSR_MISC_ENABLE, rdmsr(MSR_MISC_ENABLE) | (1<<3));
1065 #if !defined(XENPV) || defined(DOM0OPS) /* on Xen PV rdmsr is for Dom0 only */
1071 val = rdmsr(MSR_VMCR)
    [all...]
mtrr_i686.c 149 (unsigned long long)rdmsr(mtrr_raw[i].msraddr));
233 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_I686_ENABLE_MASK);
256 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_I686_ENABLE_MASK);
309 i686_mtrr_cap = rdmsr(MSR_MTRRcap);
324 mtrr_raw[i].msrval = rdmsr(mtrr_raw[i].msraddr);
powernow.c 389 status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
545 status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
555 ctl = rdmsr(MSR_AMDK7_FIDVID_CTL) & PN7_CTR_FIDCHRATIO;
582 status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
667 status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
798 status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
915 status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
  /src/sys/arch/amd64/acpi/
acpi_wakeup_low.S 142 rdmsr
147 rdmsr
152 rdmsr
157 rdmsr
acpi_wakecode.S 194 rdmsr
  /src/sys/arch/i386/i386/
longrun.c 138 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
141 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
186 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
194 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
mtrr_k6.c 90 uwccr = rdmsr(MSR_K6_UWCCR);
141 uwccr = rdmsr(MSR_K6_UWCCR);
  /src/sys/arch/i386/pci/
gcscpcib_pci.c 101 return rdmsr(msr);
  /src/sys/dev/tprof/
tprof_x86_amd.c 135 return rdmsr(PERFCTR(counter));
169 wrmsr(PERFEVTSEL(bit), rdmsr(PERFEVTSEL(bit)) | PESR_EN);
181 wrmsr(PERFEVTSEL(bit), rdmsr(PERFEVTSEL(bit)) & ~PESR_EN);
tprof_x86_intel.c 132 return rdmsr(PERFCTR(counter));
160 wrmsr(PERFEVTSEL(bit), rdmsr(PERFEVTSEL(bit)) | PERFEVTSEL_EN);
172 wrmsr(PERFEVTSEL(bit), rdmsr(PERFEVTSEL(bit)) &
  /src/sys/arch/x86/acpi/
acpi_cpu_md.c 342 val = rdmsr(MSR_CMPHALT);
451 val = rdmsr(MSR_MISC_ENABLE);
457 val = rdmsr(MSR_MISC_ENABLE);
643 sc->sc_pstate_aperf = rdmsr(MSR_APERF);
644 sc->sc_pstate_mperf = rdmsr(MSR_MPERF);
706 val = rdmsr(ps->ps_status_addr);
760 val = rdmsr(ps->ps_control_addr);
914 val = rdmsr(MSR_0FH_STATUS);
952 val = rdmsr(MSR_THERM_CONTROL);
988 val = rdmsr(MSR_THERM_CONTROL)
    [all...]
  /src/sys/dev/nvmm/x86/
nvmm_x86_vmx.c 906 msr = rdmsr(MSR_IA32_VMX_BASIC);
1864 if (exit->u.rdmsr.msr == MSR_CR_PAT) {
1870 if (exit->u.rdmsr.msr == MSR_MISC_ENABLE) {
1876 if (exit->u.rdmsr.msr == MSR_IA32_ARCH_CAPABILITIES) {
1885 val = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
1895 if (msr_ignore_list[i] != exit->u.rdmsr.msr)
1946 exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
1955 exit->u.rdmsr.npc = rip + inslen;
2113 vmx_vmwrite(VMCS_HOST_FS_BASE, rdmsr(MSR_FSBASE));
2117 cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE)
    [all...]
  /src/sys/arch/evbmips/loongson/
yeeloong_machdep.c 279 DPRINTF((" 0x%x", (uint32_t)(rdmsr(GCSC_PIC_SHDW) & 0xff)));
511 gpiobase = BONITO_PCIIO_BASE + (rdmsr(GCSC_DIVIL_LBAR_GPIO) & 0xff00);
530 wrmsr(GCSC_GLCP_SYS_RST, rdmsr(GCSC_GLCP_SYS_RST) | 1);
  /src/sys/arch/i386/acpi/
acpi_wakeup_low.S 109 rdmsr /* overwrites %edx */

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