HomeSort by: relevance | last modified time | path
    Searched refs:reg_offset (Results 1 - 25 of 60) sorted by relevancy

1 2 3

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_arct_reg_init.c 39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
41 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
42 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
47 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
48 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]))
    [all...]
amdgpu_navi10_reg_init.c 39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
40 adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i]));
41 adev->reg_offset[MMHUB_HWIP][i] = (const uint32_t *)(&(MMHUB_BASE.instance[i]));
42 adev->reg_offset[ATHUB_HWIP][i] = (const uint32_t *)(&(ATHUB_BASE.instance[i]));
43 adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIO_BASE.instance[i]));
44 adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i]));
45 adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i]));
46 adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(VCN_BASE.instance[i]));
47 adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i]));
48 adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DCN_BASE.instance[i]))
    [all...]
amdgpu_navi12_reg_init.c 39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
40 adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i]));
41 adev->reg_offset[MMHUB_HWIP][i] = (const uint32_t *)(&(MMHUB_BASE.instance[i]));
42 adev->reg_offset[ATHUB_HWIP][i] = (const uint32_t *)(&(ATHUB_BASE.instance[i]));
43 adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIF0_BASE.instance[i]));
44 adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i]));
45 adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i]));
46 adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(UVD0_BASE.instance[i]));
47 adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i]));
48 adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DMU_BASE.instance[i]))
    [all...]
amdgpu_navi14_reg_init.c 39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
40 adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i]));
41 adev->reg_offset[MMHUB_HWIP][i] = (const uint32_t *)(&(MMHUB_BASE.instance[i]));
42 adev->reg_offset[ATHUB_HWIP][i] = (const uint32_t *)(&(ATHUB_BASE.instance[i]));
43 adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIF0_BASE.instance[i]));
44 adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i]));
45 adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i]));
46 adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(UVD0_BASE.instance[i]));
47 adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i]));
48 adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DMU_BASE.instance[i]))
    [all...]
amdgpu_vega10_reg_init.c 39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
41 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
42 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
47 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
48 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]))
    [all...]
mmsch_v1_0.h 65 uint32_t reg_offset : 28; member in struct:mmsch_v1_0_cmd_direct_reg_header
70 uint32_t reg_offset : 20; member in struct:mmsch_v1_0_cmd_indirect_reg_header
103 uint32_t reg_offset,
106 direct_wt->cmd_header.reg_offset = reg_offset;
113 uint32_t reg_offset,
116 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;
125 uint32_t reg_offset,
128 direct_poll->cmd_header.reg_offset = reg_offset
    [all...]
soc15_common.h 30 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
33 WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
34 (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
38 RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
41 RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
44 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
47 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
50 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
55 uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
64 tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg);
    [all...]
amdgpu_vega20_reg_init.c 39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
41 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
42 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
47 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
48 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]))
    [all...]
amdgpu_jpeg_v1_0.c 41 static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
45 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
46 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
48 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
50 ring->ring[(*ptr)++] = reg_offset;
60 uint32_t reg, reg_offset, val, mask, i; local
64 reg_offset = (reg << 2);
66 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val)
350 uint32_t reg_offset = (reg << 2); local
394 uint32_t reg_offset = (reg << 2); local
    [all...]
soc15.h 51 uint32_t reg_offset; member in struct:soc15_reg_entry
61 uint32_t reg_offset; member in struct:soc15_allowed_register_entry
70 uint32_t reg_offset; member in struct:soc15_ras_field_entry
79 #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
amdgpu_nbio_v2_3.c 45 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
47 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
74 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
76 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
amdgpu_nbio_v7_0.c 44 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
46 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
72 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
74 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
amdgpu_jpeg_v2_0.c 605 uint32_t reg_offset = (reg << 2); local
617 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
620 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
622 amdgpu_ring_write(ring, reg_offset);
646 uint32_t reg_offset = (reg << 2); local
650 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
653 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
655 amdgpu_ring_write(ring, reg_offset);
    [all...]
amdgpu_gfx_v8_0.c 2104 u32 reg_offset; local
2109 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2110 modearray[reg_offset] = 0;
2112 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2113 mod2array[reg_offset] = 0;
2277 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++
    [all...]
amdgpu_amdkfd_gfx_v9.h 61 unsigned int reg_offset);
amdgpu_nv.c 216 u32 sh_num, u32 reg_offset)
224 val = RREG32(reg_offset);
234 u32 sh_num, u32 reg_offset)
237 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
239 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
241 return RREG32(reg_offset);
246 u32 sh_num, u32 reg_offset, u32 *value)
254 if (reg_offset !=
255 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
    [all...]
amdgpu_vcn.h 74 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
86 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
96 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \
amdgpu_soc15.c 364 u32 sh_num, u32 reg_offset)
372 val = RREG32(reg_offset);
382 u32 sh_num, u32 reg_offset)
385 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
387 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
389 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
391 return RREG32(reg_offset);
396 u32 sh_num, u32 reg_offset, u32 *value)
404 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
common_baco.h 40 uint32_t reg_offset; member in struct:baco_cmd_entry
52 uint32_t reg_offset; member in struct:soc15_baco_cmd_entry
amdgpu_common_baco.c 97 reg = entry[i].reg_offset;
117 reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg]
118 + entry[i].reg_offset;
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ni_dma.c 197 u32 reg_offset, wb_offset; local
203 reg_offset = DMA0_REGISTER_OFFSET;
207 reg_offset = DMA1_REGISTER_OFFSET;
211 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
212 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
220 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
223 WREG32(DMA_RB_RPTR + reg_offset, 0);
224 WREG32(DMA_RB_WPTR + reg_offset, 0);
227 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
229 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
    [all...]
radeon_cik_sdma.c 257 u32 rb_cntl, reg_offset; local
266 reg_offset = SDMA0_REGISTER_OFFSET;
268 reg_offset = SDMA1_REGISTER_OFFSET;
269 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
271 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
272 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);
311 uint32_t reg_offset, value; local
316 reg_offset = SDMA0_REGISTER_OFFSET;
318 reg_offset = SDMA1_REGISTER_OFFSET;
319 value = RREG32(SDMA0_CNTL + reg_offset);
338 u32 me_cntl, reg_offset; local
375 u32 reg_offset, wb_offset; local
    [all...]
  /src/sys/dev/isa/
nca_isa.c 123 nca_isa_test(bus_space_tag_t iot, bus_space_handle_t ioh, bus_size_t reg_offset)
127 bus_space_write_1(iot, ioh, reg_offset + C80_ICR, SCI_ICMD_RST);
128 bus_space_write_1(iot, ioh, reg_offset + C80_ODR, 0);
132 if (bus_space_read_1(iot, ioh, reg_offset + C80_CSBR) != SCI_BUS_RST) {
135 __func__, bus_space_read_1(iot, ioh, reg_offset+C80_CSBR));
137 bus_space_write_1(iot, ioh, reg_offset+C80_ICR, 0);
141 bus_space_write_1(iot, ioh, reg_offset + C80_ICR, 0);
146 bus_space_read_1(iot, ioh, reg_offset + C80_RPIR);
150 if (bus_space_read_1(iot, ioh, reg_offset + C80_BSR) & (SCI_CSR_PERR |
154 __func__, bus_space_read_1(iot, ioh, reg_offset+C80_BSR))
179 bus_size_t base_offset, reg_offset = 0; local
    [all...]
  /src/usr.bin/scmdctl/
common.c 221 uint8_t reg, reg_index = 0, reg_offset = 0; local
241 reg_offset = motor_index / 8;
244 reg = SCMD_REG_INV_2_9 + reg_offset;
246 fprintf(stderr,"common_invert_motor: remote invert: motor_index: %d ; reg_offset: %d ; reg_index: %02X ; reg: %02X\n",motor_index,reg_offset,reg_index,reg);
263 uint8_t reg, reg_index = 0, reg_offset = 0; local
276 reg_offset = module_index / 8;
279 reg = SCMD_REG_BRIDGE_SLV_L + reg_offset;
281 fprintf(stderr,"common_bridge_motor: remote bridge: module_index: %d ; reg_offset: %d ; reg_index: %02X ; reg: %02X\n",module_index,reg_offset,reg_index,reg)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/
kfd_pm4_headers_diq.h 192 unsigned int reg_offset:16; member in struct:pm4__set_config_reg::__anon4437::__anon4438

Completed in 45 milliseconds

1 2 3