1 /* $NetBSD: sbbrz_pci.c,v 1.8 2017/07/24 09:56:46 mrg Exp $ */ 2 3 /* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. Neither the "Broadcom Corporation" name nor any 19 * trademark or logo of Broadcom Corporation may be used to endorse or 20 * promote products derived from this software without the prior written 21 * permission of Broadcom Corporation. 22 * 23 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 26 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 27 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 28 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* from: $NetBSD: apecs_pci.c,v 1.18 2000/06/29 08:58:45 mrg Exp */ 37 38 /* 39 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 40 * All rights reserved. 41 * 42 * Author: Chris G. Demetriou 43 * 44 * Permission to use, copy, modify and distribute this software and 45 * its documentation is hereby granted, provided that both the copyright 46 * notice and this permission notice appear in all copies of the 47 * software, derivative works or modified versions, and any portions 48 * thereof, and that both notices appear in supporting documentation. 49 * 50 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 51 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 52 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 53 * 54 * Carnegie Mellon requests users of this software to return to 55 * 56 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 57 * School of Computer Science 58 * Carnegie Mellon University 59 * Pittsburgh PA 15213-3890 60 * 61 * any improvements or extensions that they make and grant Carnegie the 62 * rights to redistribute these changes. 63 */ 64 65 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 66 67 __KERNEL_RCSID(0, "$NetBSD: sbbrz_pci.c,v 1.8 2017/07/24 09:56:46 mrg Exp $"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/kernel.h> 72 #include <sys/device.h> 73 #include <uvm/uvm_extern.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 78 #include <mips/locore.h> 79 #include <mips/sibyte/include/sb1250_regs.h> 80 #include <mips/sibyte/include/sb1250_scd.h> 81 #include <mips/sibyte/include/sb1250_int.h> 82 #include <mips/sibyte/pci/sbbrzvar.h> 83 84 #include <evbmips/sbmips/systemsw.h> 85 86 void sbbrz_pci_attach_hook(device_t, device_t, 87 struct pcibus_attach_args *); 88 static int sbbrz_pci_bus_maxdevs(void *, int); 89 static pcitag_t sbbrz_pci_make_tag(void *, int, int, int); 90 static void sbbrz_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 91 92 static pcireg_t sbbrz_pci_conf_read(void *, pcitag_t, int); 93 static void sbbrz_pci_conf_write(void *, pcitag_t, int, pcireg_t); 94 #ifdef PCI_NETBSD_CONFIGURE 95 static void sbbrz_pci_conf_interrupt(void *, int, int, int, int, int *); 96 #endif 97 98 static int sbbrz_pci_intr_map(const struct pci_attach_args *, 99 pci_intr_handle_t *); 100 static const char * 101 sbbrz_pci_intr_string(void *, pci_intr_handle_t, char *, size_t); 102 static const struct evcnt * 103 sbbrz_pci_intr_evcnt(void *, pci_intr_handle_t); 104 static void * sbbrz_pci_intr_establish(void *, pci_intr_handle_t, 105 int, int (*)(void *), void *); 106 static void sbbrz_pci_intr_disestablish(void *, void *); 107 108 109 void 110 sbbrz_pci_init(pci_chipset_tag_t pc, void *v) 111 { 112 113 pc->pc_conf_v = v; 114 pc->pc_attach_hook = sbbrz_pci_attach_hook; 115 pc->pc_bus_maxdevs = sbbrz_pci_bus_maxdevs; 116 pc->pc_make_tag = sbbrz_pci_make_tag; 117 pc->pc_decompose_tag = sbbrz_pci_decompose_tag; 118 pc->pc_conf_read = sbbrz_pci_conf_read; 119 pc->pc_conf_write = sbbrz_pci_conf_write; 120 pc->pc_intr_map = sbbrz_pci_intr_map; 121 pc->pc_intr_string = sbbrz_pci_intr_string; 122 pc->pc_intr_evcnt = sbbrz_pci_intr_evcnt; 123 pc->pc_intr_establish = sbbrz_pci_intr_establish; 124 pc->pc_intr_disestablish = sbbrz_pci_intr_disestablish; 125 #ifdef PCI_NETBSD_CONFIGURE 126 pc->pc_conf_interrupt = sbbrz_pci_conf_interrupt; 127 #endif 128 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 129 pc->pc_pciide_compat_intr_establish = sbbrz_pciide_compat_intr_establish; 130 #endif 131 } 132 133 void 134 sbbrz_pci_attach_hook(device_t parent, device_t self, 135 struct pcibus_attach_args *pba) 136 { 137 } 138 139 int 140 sbbrz_pci_bus_maxdevs(void *cpv, int busno) 141 { 142 uint64_t regval; 143 int host; 144 145 /* If not the PCI bus directly off the 1250, always up to 32 devs. */ 146 if (busno != 0) 147 return 32; 148 149 /* If the PCI on the 1250, 32 devices if host mode, otherwise only 2. */ 150 regval = mips3_ld((register_t)MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG)); 151 host = (regval & M_SYS_PCI_HOST) != 0; 152 153 return (host ? 32 : 2); 154 } 155 156 pcitag_t 157 sbbrz_pci_make_tag(void *cpv, int b, int d, int f) 158 { 159 160 return (b << 16) | (d << 11) | (f << 8); 161 } 162 163 void 164 sbbrz_pci_decompose_tag(void *cpv, pcitag_t tag, 165 int *bp, int *dp, int *fp) 166 { 167 168 if (bp != NULL) 169 *bp = (tag >> 16) & 0xff; 170 if (dp != NULL) 171 *dp = (tag >> 11) & 0x1f; 172 if (fp != NULL) 173 *fp = (tag >> 8) & 0x7; 174 } 175 176 pcireg_t 177 sbbrz_pci_conf_read(void *cpv, pcitag_t tag, int offset) 178 { 179 uint64_t addr; 180 181 #ifdef DIAGNOSTIC 182 if ((offset & 0x3) != 0) 183 panic ("pci_conf_read: misaligned"); 184 #endif 185 186 if ((unsigned int)offset >= PCI_CONF_SIZE) 187 return 0xffffffff; 188 189 addr = A_PHYS_LDTPCI_CFG_MATCH_BITS + tag + offset; 190 addr = MIPS_PHYS_TO_XKPHYS(MIPS3_TLB_ATTR_UNCACHED, addr); 191 192 __asm volatile("sync"); 193 194 if (badaddr64(addr, 4) != 0) 195 return 0xffffffff; 196 197 return mips3_ld(addr); 198 } 199 200 void 201 sbbrz_pci_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data) 202 { 203 uint64_t addr; 204 205 #ifdef DIAGNOSTIC 206 if ((offset & 0x3) != 0) 207 panic ("pci_conf_write: misaligned"); 208 #endif 209 210 if ((unsigned int)offset >= PCI_CONF_SIZE) 211 return; 212 213 addr = A_PHYS_LDTPCI_CFG_MATCH_BITS + tag + offset; 214 addr = MIPS_PHYS_TO_XKPHYS(MIPS3_TLB_ATTR_UNCACHED, addr); 215 216 return mips3_sd(addr, data); 217 } 218 219 int 220 sbbrz_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 221 { 222 int bus, device, func; 223 sbbrz_pci_decompose_tag(NULL, pa->pa_intrtag, &bus, &device, &func); 224 *ihp = 0; 225 if (pa->pa_intrpin == PCI_INTERRUPT_PIN_NONE) 226 return EINVAL; 227 if (bus == 0) { 228 *ihp = K_INT_PCI_INTA 229 + (((device-5) + pa->pa_intrswiz + pa->pa_intrpin - PCI_INTERRUPT_PIN_A) % 4); 230 return 0; 231 } 232 return EOPNOTSUPP; 233 } 234 235 const char * 236 sbbrz_pci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 237 { 238 char c; 239 240 switch (ih) { 241 default: c = '?'; break; 242 case K_INT_PCI_INTA: c = 'a'; break; 243 case K_INT_PCI_INTB: c = 'b'; break; 244 case K_INT_PCI_INTC: c = 'c'; break; 245 case K_INT_PCI_INTD: c = 'd'; break; 246 } 247 snprintf(buf, len, "pci int%c", c); 248 return buf; 249 } 250 251 const struct evcnt * 252 sbbrz_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 253 { 254 return NULL; 255 } 256 257 void * 258 sbbrz_pci_intr_establish(void *v, pci_intr_handle_t ih, int level, 259 int (*handler)(void *), void *arg) 260 { 261 return cpu_intr_establish(ih, level, 262 (void (*)(void *, uint32_t, vaddr_t))handler, arg); 263 } 264 265 void 266 sbbrz_pci_intr_disestablish(void *v, void *ih) 267 { 268 } 269
Indexes created Sun Sep 28 07:09:56 GMT 2025