| /src/sys/arch/amiga/dev/ |
| sci.c | 270 device_xname(dev->sc_dev), where, *dev->sci_csr, *dev->sci_bus_csr);
380 if ((*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) &&
381 (*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) &&
382 (*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)))
388 while ((*dev->sci_bus_csr & SCI_BUS_BSY) == 0) {
418 csr = *dev->sci_bus_csr;
429 csr = *dev->sci_bus_csr;
437 while (*dev->sci_bus_csr & SCI_BUS_REQ);
450 volatile register u_char *sci_bus_csr = dev->sci_bus_csr; local in function:sci_ixfer_in
[all...] |
| wstsc.c | 150 sc->sci_bus_csr = rp + 8;
214 QPRINTF(("supradma_in %d, csr=%02x\n", len, *dev->sci_bus_csr));
226 || !(*dev->sci_bus_csr & SCI_BUS_BSY)
231 len, *dev->sci_bus_csr, wait);
263 || !(*dev->sci_bus_csr & SCI_BUS_BSY)
268 len, *dev->sci_bus_csr, wait);
295 QPRINTF(("supradma_out %d, csr=%02x\n", len, *dev->sci_bus_csr));
310 || !(*dev->sci_bus_csr & SCI_BUS_BSY)
315 len, *dev->sci_bus_csr, wait);
351 QPRINTF(("supradma_in2 %d, csr=%02x\n", len, *dev->sci_bus_csr));
431 volatile register u_char *sci_bus_csr = dev->sci_bus_csr; local in function:wstsc_dma_xfer_out2
[all...] |
| scireg.h | 58 volatile unsigned char sci_bus_csr; /* r: Bus Status */
59 #define sci_sel_enb sci_bus_csr /* w: Select enable */
|
| otgsc.c | 138 sc->sci_bus_csr = rp + 0x40;
196 QPRINTF(("otgsc_dma_in %d, csr=%02x\n", len, *dev->sci_bus_csr));
207 || !(*dev->sci_bus_csr & SCI_BUS_BSY)
212 len, *dev->sci_bus_csr, wait);
239 QPRINTF(("otgsc_dma_out %d, csr=%02x\n", len, *dev->sci_bus_csr));
254 || !(*dev->sci_bus_csr & SCI_BUS_BSY)
259 len, *dev->sci_bus_csr, wait);
|
| ivsc.c | 143 sc->sci_bus_csr = rp + 8;
203 QPRINTF(("ivsc_dma_in %d, csr=%02x\n", len, *dev->sci_bus_csr));
214 || !(*dev->sci_bus_csr & SCI_BUS_BSY)
219 len, *dev->sci_bus_csr, wait);
251 || !(*dev->sci_bus_csr & SCI_BUS_BSY)
256 len, *dev->sci_bus_csr, wait);
283 QPRINTF(("ivsc_dma_out %d, csr=%02x\n", len, *dev->sci_bus_csr));
298 || !(*dev->sci_bus_csr & SCI_BUS_BSY)
303 len, *dev->sci_bus_csr, wait);
|
| mlhsc.c | 136 sc->sci_bus_csr = rp + 9;
190 csr = *dev->sci_bus_csr;
204 || !(*dev->sci_bus_csr & SCI_BUS_BSY)
240 || !(*dev->sci_bus_csr & SCI_BUS_BSY)
273 csr = *dev->sci_bus_csr;
291 || !(*dev->sci_bus_csr & SCI_BUS_BSY)
319 || !(*dev->sci_bus_csr & SCI_BUS_BSY)
|
| scivar.h | 53 volatile u_char *sci_bus_csr; /* r: Bus Status */ member in struct:sci_softc
|
| empsc.c | 138 sc->sci_bus_csr = rp + 0x40;
|
| /src/sys/arch/mac68k/include/ |
| scsi_5380.h | 54 volatile unsigned char sci_bus_csr; /* r: Bus Status */ member in struct:__anon111e084b0108
55 #define sci_sel_enb sci_bus_csr /* w: Select enable */
|
| /src/sys/dev/ic/ |
| ncr5380reg.h | 80 #define sci_bus_csr sci_r4 /* r: Bus Status */ macro
137 * R4: Current (SCSI) Bus status (.sci_bus_csr)
|
| ncr5380sbc.c | 197 if (NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) {
215 if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0) {
264 if (SCI_BUS_PHASE(NCR5380_READ(sc, sci_bus_csr)) != phase)
320 if (SCI_BUS_PHASE(NCR5380_READ(sc, sci_bus_csr)) != phase)
1091 bus = NCR5380_READ(sc, sci_bus_csr);
1118 bus = NCR5380_READ(sc, sci_bus_csr);
1171 bus = NCR5380_READ(sc, sci_bus_csr);
1202 phase = SCI_BUS_PHASE(NCR5380_READ(sc, sci_bus_csr));
1459 if (NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_BSY)
1477 if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_BSY) == 0)
[all...] |
| ncr5380var.h | 77 #define SCI_BUSY(sc) (NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_BSY)
|
| /src/sys/arch/mac68k/dev/ |
| sbc.c | 187 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) {
208 u_int8_t bus_csr = *ncr_sc->sci_bus_csr;
630 *ncr_sc->sci_bus_csr);
819 *ncr_sc->sci_bus_csr);
|
| /src/sys/dev/podulebus/ |
| hcsc.c | 255 if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 ||
|
| oak.c | 270 if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 ||
|
