| /src/sys/arch/amiga/dev/ |
| otgsc.c | 140 sc->sci_csr = rp + 0x50;
191 volatile register u_char *sci_csr = dev->sci_csr; local in function:otgsc_dma_xfer_in
204 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
206 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
237 volatile register u_char *sci_csr = dev->sci_csr; local in function:otgsc_dma_xfer_out
251 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
253 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
271 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) =
[all...] |
| mlhsc.c | 138 sc->sci_csr = rp + 11;
185 volatile register u_char *sci_csr = dev->sci_csr; local in function:mlhsc_dma_xfer_in
201 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
203 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
237 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
239 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
271 volatile register u_char *sci_csr = dev->sci_csr; local in function:mlhsc_dma_xfer_out
288 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !
[all...] |
| wstsc.c | 152 sc->sci_csr = rp + 10;
209 volatile register u_char *sci_csr = dev->sci_csr; local in function:wstsc_dma_xfer_in
223 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
225 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
260 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
262 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
293 volatile register u_char *sci_csr = dev->sci_csr; local in function:wstsc_dma_xfer_out
307 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !
343 volatile register u_char *sci_csr = dev->sci_csr + 0x10; local in function:wstsc_dma_xfer_in2
[all...] |
| ivsc.c | 145 sc->sci_csr = rp + 10;
198 volatile register u_char *sci_csr = dev->sci_csr; local in function:ivsc_dma_xfer_in
211 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
213 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
248 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
250 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
281 volatile register u_char *sci_csr = dev->sci_csr; local in function:ivsc_dma_xfer_out
295 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !
[all...] |
| scireg.h | 62 volatile unsigned char sci_csr; /* r: Status */
63 #define sci_dma_send sci_csr /* w: Start DMA send data */
|
| empsc.c | 140 sc->sci_csr = rp + 0x50;
187 if ((*dev->sci_csr & SCI_CSR_INT) == 0)
|
| scivar.h | 55 volatile u_char *sci_csr; /* r: Status */ member in struct:sci_softc
|
| sci.c | 270 device_xname(dev->sc_dev), where, *dev->sci_csr, *dev->sci_bus_csr);
432 if (!(*dev->sci_csr & SCI_CSR_PHASE_MATCH))
479 if (!(*dev->sci_csr & SCI_CSR_PHASE_MATCH))
|
| /src/sys/arch/mac68k/include/ |
| scsi_5380.h | 58 volatile unsigned char sci_csr; /* r: Status */ member in struct:__anon111e084b0108
59 #define sci_dma_send sci_csr /* w: Start DMA send data */
|
| /src/sys/arch/mac68k/dev/ |
| sbc.c | 135 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
140 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0)
158 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
178 if (*ncr_sc->sci_csr & SCI_CSR_INT) {
186 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT)
207 u_int8_t csr = *ncr_sc->sci_csr;
400 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) {
560 if (*ncr_sc->sci_csr & SCI_CSR_ACK)
629 device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr,
818 device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr,
[all...] |
| /src/sys/dev/ic/ |
| ncr5380reg.h | 83 #define sci_csr sci_r5 /* r: Status */ macro
151 * R5: Bus and Status register (.sci_csr)
|
| ncr5380sbc.c | 1614 if (NCR5380_READ(sc, sci_csr) & SCI_CSR_PERR) {
2318 if (NCR5380_READ(sc, sci_csr) & SCI_CSR_PERR) {
|
| /src/sys/dev/podulebus/ |
| hcsc.c | 234 if ((NCR5380_READ(sc,sci_csr) &
239 if ((NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 ||
256 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 ||
355 if ((NCR5380_READ(ncr_sc, sci_csr)
|
| oak.c | 232 status = NCR5380_READ(sc, sci_csr);
271 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 ||
375 if ((NCR5380_READ(ncr_sc, sci_csr)
|
