HomeSort by: relevance | last modified time | path
    Searched refs:sclk_dpm_enable_mask (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
smu7_hwmgr.h 169 uint32_t sclk_dpm_enable_mask; member in struct:smu7_dpmlevel_enable_mask
vega10_hwmgr.h 179 uint32_t sclk_dpm_enable_mask; member in struct:vega10_dpmlevel_enable_mask
vega12_hwmgr.h 157 uint32_t sclk_dpm_enable_mask; member in struct:vega12_dpmlevel_enable_mask
vega20_hwmgr.h 210 uint32_t sclk_dpm_enable_mask; member in struct:vega20_dpmlevel_enable_mask
amdgpu_smu7_hwmgr.c 2625 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2627 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
2664 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
2667 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2702 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2704 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3867 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4421 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4997 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4999 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
ci_dpm.h 113 u32 sclk_dpm_enable_mask; member in struct:ci_dpm_level_enable_mask
radeon_ci_dpm.c 3311 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3829 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3832 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4184 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4240 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4242 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4279 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4281 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_vegam_smumgr.c 912 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
917 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1;
amdgpu_fiji_smumgr.c 1050 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
amdgpu_iceland_smumgr.c 1007 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
amdgpu_ci_smumgr.c 505 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
amdgpu_polaris10_smumgr.c 1025 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
amdgpu_tonga_smumgr.c 737 data->dpm_level_enable_mask.sclk_dpm_enable_mask =

Completed in 35 milliseconds