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    Searched refs:sdma_offsets (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v2_4.c 66 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
216 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
232 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
357 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
359 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
360 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
362 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
399 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
404 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
432 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0)
    [all...]
amdgpu_sdma_v3_0.c 80 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
378 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
405 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
531 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
533 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
534 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
536 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
592 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
599 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
601 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i]
    [all...]
amdgpu_cik_sdma.c 52 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
188 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
202 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
323 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
325 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
326 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
382 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
387 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
389 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
397 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl)
    [all...]
amdgpu_si_dma.c 35 const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
56 return (RREG32(DMA_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
64 WREG32(DMA_RB_WPTR + sdma_offsets[me],
126 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]);
128 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl);
146 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
147 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
155 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl);
158 WREG32(DMA_RB_RPTR + sdma_offsets[i], 0);
159 WREG32(DMA_RB_WPTR + sdma_offsets[i], 0)
    [all...]

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