| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| gfx_v9_0.h | 31 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
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| soc15.h | 53 uint32_t se_num; member in struct:soc15_reg_entry
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| amdgpu_nv.c | 215 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
221 if (se_num != 0xffffffff || sh_num != 0xffffffff)
222 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
226 if (se_num != 0xffffffff || sh_num != 0xffffffff)
233 bool indexed, u32 se_num,
237 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
245 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
260 se_num, sh_num, reg_offset);
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| amdgpu_soc15.c | 363 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
369 if (se_num != 0xffffffff || sh_num != 0xffffffff)
370 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
374 if (se_num != 0xffffffff || sh_num != 0xffffffff)
381 bool indexed, u32 se_num,
385 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
395 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
410 se_num, sh_num, reg_offset);
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| amdgpu_vi.c | 559 bool indexed, u32 se_num,
564 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
579 if (se_num != 0xffffffff || sh_num != 0xffffffff)
580 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
584 if (se_num != 0xffffffff || sh_num != 0xffffffff)
654 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
666 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
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| amdgpu_gfx_v9_4.c | 98 static void gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num,
110 if (se_num == 0xffffffff)
114 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
875 for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) {
907 for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) {
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| amdgpu_cik.c | 1054 bool indexed, u32 se_num,
1059 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
1074 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1075 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1079 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1149 static int cik_read_register(struct amdgpu_device *adev, u32 se_num,
1161 *value = cik_get_register_value(adev, indexed, se_num, sh_num,
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| amdgpu_si.c | 1036 bool indexed, u32 se_num,
1041 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
1054 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1055 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1059 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1110 static int si_read_register(struct amdgpu_device *adev, u32 se_num,
1122 *value = si_get_register_value(adev, indexed, se_num, sh_num,
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| amdgpu_gfx.h | 195 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
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| amdgpu_kms.c | 657 unsigned se_num = (info->read_mmr_reg.instance >> local in function:amdgpu_info_ioctl
666 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
667 se_num = 0xffffffff;
681 if (amdgpu_asic_read_register(adev, se_num, sh_num,
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| amdgpu_gfx_v6_0.c | 1306 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1316 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1319 else if (se_num == 0xffffffff)
1324 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1327 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
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| amdgpu.h | 577 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
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| amdgpu_gfx_v7_0.c | 1589 * @se_num: shader engine to address
1597 u32 se_num, u32 sh_num, u32 instance)
1606 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1609 else if (se_num == 0xffffffff)
1614 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1617 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1790 * @se_num: number of SEs (shader engines) for the asic
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| amdgpu_gfx_v9_0.c | 743 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
2337 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
2346 if (se_num == 0xffffffff)
2349 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
6338 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) {
6400 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) {
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| amdgpu_gfx_v10_0.c | 256 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1495 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1507 if (se_num == 0xffffffff)
1511 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
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| amdgpu_gfx_v8_0.c | 3423 u32 se_num, u32 sh_num, u32 instance)
3432 if (se_num == 0xffffffff)
3435 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_si.c | 2959 u32 se_num, u32 sh_num)
2963 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
2965 else if (se_num == 0xffffffff)
2968 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
2970 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
3004 u32 se_num, u32 sh_per_se,
3010 for (i = 0; i < se_num; i++) {
3051 u32 se_num, u32 sh_per_se,
3059 for (i = 0; i < se_num; i++) {
3069 for (i = 0; i < max_rb_num_per_se * se_num; i++)
[all...] |
| radeon_cik.c | 3045 * @se_num: shader engine to address
3053 u32 se_num, u32 sh_num)
3057 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
3059 else if (se_num == 0xffffffff)
3062 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
3064 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
3092 * @se_num: number of SEs (shader engines) for the asic
3122 * @se_num: number of SEs (shader engines) for the asic
3129 u32 se_num, u32 sh_per_se,
3137 for (i = 0; i < se_num; i++)
[all...] |
