/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
gfx_v9_0.h | 31 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
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amdgpu_nv.c | 216 u32 sh_num, u32 reg_offset) 221 if (se_num != 0xffffffff || sh_num != 0xffffffff) 222 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 226 if (se_num != 0xffffffff || sh_num != 0xffffffff) 234 u32 sh_num, u32 reg_offset) 237 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 246 u32 sh_num, u32 reg_offset, u32 *value) 260 se_num, sh_num, reg_offset);
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amdgpu_soc15.c | 364 u32 sh_num, u32 reg_offset) 369 if (se_num != 0xffffffff || sh_num != 0xffffffff) 370 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 374 if (se_num != 0xffffffff || sh_num != 0xffffffff) 382 u32 sh_num, u32 reg_offset) 385 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 396 u32 sh_num, u32 reg_offset, u32 *value) 410 se_num, sh_num, reg_offset);
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amdgpu_vi.c | 560 u32 sh_num, u32 reg_offset) 565 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; 579 if (se_num != 0xffffffff || sh_num != 0xffffffff) 580 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 584 if (se_num != 0xffffffff || sh_num != 0xffffffff) 655 u32 sh_num, u32 reg_offset, u32 *value) 666 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
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amdgpu_cik.c | 1055 u32 sh_num, u32 reg_offset) 1060 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; 1074 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1075 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 1079 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1150 u32 sh_num, u32 reg_offset, u32 *value) 1161 *value = cik_get_register_value(adev, indexed, se_num, sh_num,
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amdgpu_si.c | 1037 u32 sh_num, u32 reg_offset) 1042 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; 1054 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1055 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 1059 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1111 u32 sh_num, u32 reg_offset, u32 *value) 1122 *value = si_get_register_value(adev, indexed, se_num, sh_num,
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amdgpu_gfx.h | 196 u32 sh_num, u32 instance);
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amdgpu_gfx_v9_4.c | 99 u32 sh_num, u32 instance) 116 if (sh_num == 0xffffffff) 120 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
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amdgpu_kms.c | 660 unsigned sh_num = (info->read_mmr_reg.instance >> local in function:amdgpu_info_ioctl 668 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 669 sh_num = 0xffffffff; 681 if (amdgpu_asic_read_register(adev, se_num, sh_num,
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amdgpu_gfx_v6_0.c | 1307 u32 sh_num, u32 instance) 1316 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1321 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1322 else if (sh_num == 0xffffffff) 1326 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
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amdgpu.h | 578 u32 sh_num, u32 reg_offset, u32 *value);
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amdgpu_gfx_v7_0.c | 1590 * @sh_num: sh block to address 1597 u32 se_num, u32 sh_num, u32 instance) 1606 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1611 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1612 else if (sh_num == 0xffffffff) 1616 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
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amdgpu_gfx_v10_0.c | 257 u32 sh_num, u32 instance); 1496 u32 sh_num, u32 instance) 1513 if (sh_num == 0xffffffff) 1517 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
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amdgpu_gfx_v9_0.c | 743 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 2337 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) 2351 if (sh_num == 0xffffffff) 2354 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
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amdgpu_gfx_v8_0.c | 3423 u32 se_num, u32 sh_num, u32 instance) 3437 if (sh_num == 0xffffffff) 3440 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
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/src/sys/external/bsd/drm2/dist/drm/radeon/ |
radeon_si.c | 2959 u32 se_num, u32 sh_num) 2963 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 2966 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); 2967 else if (sh_num == 0xffffffff) 2970 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
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radeon_cik.c | 3046 * @sh_num: sh block to address 3053 u32 se_num, u32 sh_num) 3057 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 3060 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); 3061 else if (sh_num == 0xffffffff) 3064 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
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