HomeSort by: relevance | last modified time | path
    Searched refs:smc_state_table (Results 1 - 24 of 24) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
fiji_smumgr.h 44 struct SMU73_Discrete_DpmTable smc_state_table; member in struct:fiji_smumgr
ci_smumgr.h 70 struct SMU7_Discrete_DpmTable smc_state_table; member in struct:ci_smumgr
iceland_smumgr.h 64 struct SMU71_Discrete_DpmTable smc_state_table; member in struct:iceland_smumgr
polaris10_smumgr.h 59 SMU74_Discrete_DpmTable smc_state_table; member in struct:polaris10_smumgr
tonga_smumgr.h 68 struct SMU72_Discrete_DpmTable smc_state_table; member in struct:tonga_smumgr
vegam_smumgr.h 68 SMU75_Discrete_DpmTable smc_state_table; member in struct:vegam_smumgr
amdgpu_fiji_smumgr.c 497 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
854 smu_data->smc_state_table.LinkLevelCount =
1022 smu_data->smc_state_table.GraphicsLevel;
1048 smu_data->smc_state_table.GraphicsDpmLevelCount =
1238 smu_data->smc_state_table.MemoryLevel;
1263 smu_data->smc_state_table.MemoryDpmLevelCount =
1651 smu_data->smc_state_table.GraphicsBootLevel = level;
1660 smu_data->smc_state_table.MemoryBootLevel = level;
1705 smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
1709 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |
    [all...]
amdgpu_tonga_smumgr.c 535 smu_data->smc_state_table.LinkLevelCount =
705 SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
718 &(smu_data->smc_state_table.GraphicsLevel[i]));
724 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
728 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
732 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
735 smu_data->smc_state_table.GraphicsDpmLevelCount =
746 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
776 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
779 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled
    [all...]
amdgpu_iceland_smumgr.c 792 smu_data->smc_state_table.LinkLevelCount =
975 SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
988 &(smu_data->smc_state_table.GraphicsLevel[i]));
994 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
998 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1002 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
1005 smu_data->smc_state_table.GraphicsDpmLevelCount =
1032 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
1036 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
1039 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled
    [all...]
amdgpu_vegam_smumgr.c 343 smu_data->smc_state_table.UvdBootLevel = 0;
345 smu_data->smc_state_table.UvdBootLevel =
354 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
364 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
377 smu_data->smc_state_table.VceBootLevel =
380 smu_data->smc_state_table.VceBootLevel = 0;
389 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
396 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
594 smu_data->smc_state_table.LinkLevelCount =
725 const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
    [all...]
amdgpu_ci_smumgr.c 486 smu_data->smc_state_table.GraphicsLevel;
496 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
498 smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark =
502 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
504 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
723 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
1018 smu_data->smc_state_table.LinkLevelCount =
1314 SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
1323 &(smu_data->smc_state_table.MemoryLevel[i]));
1328 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1
    [all...]
amdgpu_polaris10_smumgr.c 434 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
792 smu_data->smc_state_table.LinkLevelCount =
850 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
997 smu_data->smc_state_table.GraphicsLevel;
1004 polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
1010 &(smu_data->smc_state_table.GraphicsLevel[i]));
1020 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1022 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1023 smu_data->smc_state_table.GraphicsDpmLevelCount =
1141 smu_data->smc_state_table.MemoryLevel
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_vega10_hwmgr.c 961 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1480 data->smc_state_table.pp_table.UlvOffsetVid =
1483 data->smc_state_table.pp_table.UlvSmnclkDid =
1485 data->smc_state_table.pp_table.UlvMp1clkDid =
1487 data->smc_state_table.pp_table.UlvGfxclkBypass =
1489 data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =
1491 data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =
1518 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1676 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1731 PPTable_t *pp_table = &(data->smc_state_table.pp_table)
    [all...]
amdgpu_vega10_thermal.c 512 PPTable_t *table = &(data->smc_state_table.pp_table);
556 (uint8_t *)(&(data->smc_state_table.pp_table)),
567 PPTable_t *table = &(data->smc_state_table.pp_table);
581 (uint8_t *)(&(data->smc_state_table.pp_table)),
amdgpu_vega20_thermal.c 126 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
333 PPTable_t *table = &(data->smc_state_table.pp_table);
amdgpu_vega12_thermal.c 263 PPTable_t *table = &(data->smc_state_table.pp_table);
vega10_hwmgr.h 383 struct vega10_smc_state_table smc_state_table; member in struct:vega10_hwmgr
vega12_hwmgr.h 395 struct vega12_smc_state_table smc_state_table; member in struct:vega12_hwmgr
vega20_hwmgr.h 524 struct vega20_smc_state_table smc_state_table; member in struct:vega20_hwmgr
amdgpu_vega20_hwmgr.c 797 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1025 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1226 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1327 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
2901 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2924 &(data->smc_state_table.overdrive_table);
3267 &(data->smc_state_table.overdrive_table);
3557 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
4130 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
amdgpu_vega12_hwmgr.c 739 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1871 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2379 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2588 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
amdgpu_vega10_powertune.c 1296 PPTable_t *table = &(data->smc_state_table.pp_table);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ci_dpm.c 439 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
1309 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
2602 pi->smc_state_table.GraphicsBootLevel = level;
2610 pi->smc_state_table.MemoryBootLevel = level;
2649 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
3290 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3299 &pi->smc_state_table.GraphicsLevel[i]);
3303 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3305 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3308 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1
    [all...]
ci_dpm.h 226 SMU7_Discrete_DpmTable smc_state_table; member in struct:ci_power_info

Completed in 180 milliseconds