| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| fiji_smumgr.h | 43 struct smu7_smumgr smu7_data; member in struct:fiji_smumgr
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| iceland_smumgr.h | 63 struct smu7_smumgr smu7_data; member in struct:iceland_smumgr
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| polaris10_smumgr.h | 57 struct smu7_smumgr smu7_data; member in struct:polaris10_smumgr
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| tonga_smumgr.h | 67 struct smu7_smumgr smu7_data; member in struct:tonga_smumgr
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| vegam_smumgr.h | 66 struct smu7_smumgr smu7_data; member in struct:vegam_smumgr
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| amdgpu_fiji_smumgr.c | 316 &(priv->smu7_data.soft_regs_start), 0x40000);
1017 uint32_t array = smu_data->smu7_data.dpm_table_start +
1233 uint32_t array = smu_data->smu7_data.dpm_table_start +
1553 smu_data->smu7_data.arb_table_start,
1884 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
1893 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
2112 smu_data->smu7_data.dpm_table_start +
2153 if (smu_data->smu7_data.fan_table_start == 0) {
2219 res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
2284 smu_data->smu7_data.dpm_table_start
[all...] |
| amdgpu_iceland_smumgr.c | 258 &(priv->smu7_data.soft_regs_start), 0x40000);
969 uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start +
1359 uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel);
1642 smu_data->smu7_data.arb_table_start,
1799 address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
1821 return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
2062 result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start +
2073 smu_data->smu7_data.ulv_setting_starts,
2092 struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend); local in function:iceland_thermal_setup_fan_table
2110 if (0 == smu7_data->fan_table_start)
2285 struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend); local in function:iceland_process_firmware_header
[all...] |
| amdgpu_vegam_smumgr.c | 206 smu_data->smu7_data.security_hard_key = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(
222 &(smu_data->smu7_data.soft_regs_start),
244 smu_data->smu7_data.dpm_table_start = tmp;
255 smu_data->smu7_data.soft_regs_start = tmp;
266 smu_data->smu7_data.mc_reg_table_start = tmp;
274 smu_data->smu7_data.fan_table_start = tmp;
284 smu_data->smu7_data.arb_table_start = tmp;
347 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable,
382 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
876 uint32_t array = smu_data->smu7_data.dpm_table_start
[all...] |
| amdgpu_polaris10_smumgr.c | 304 smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
320 &(smu_data->smu7_data.soft_regs_start), 0x40000);
992 uint32_t array = smu_data->smu7_data.dpm_table_start +
1136 uint32_t array = smu_data->smu7_data.dpm_table_start +
1390 smu_data->smu7_data.arb_table_start,
1634 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
1796 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
1805 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
2019 smu_data->smu7_data.dpm_table_start +
2087 if (smu_data->smu7_data.fan_table_start == 0)
[all...] |
| amdgpu_tonga_smumgr.c | 225 &(priv->smu7_data.soft_regs_start), 0x40000);
699 uint32_t level_array_address = smu_data->smu7_data.dpm_table_start +
1101 smu_data->smu7_data.dpm_table_start +
1517 smu_data->smu7_data.arb_table_start,
1818 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
1827 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
2178 address = smu_data->smu7_data.mc_reg_table_start +
2205 return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
2442 smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags),
2487 if (0 == smu_data->smu7_data.fan_table_start)
[all...] |
