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  /src/sys/arch/evbmips/atheros/
wdog.c 135 sc->sc_smw.smw_period = sc->sc_wdog_period;
161 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
162 smw->smw_period = sc->sc_wdog_period;
163 else if (smw->smw_period != sc->sc_wdog_period) {
168 if (smw->smw_period > sc->sc_wdog_max) {
171 sc->sc_wdog_period = smw->smw_period;
  /src/sys/arch/mips/adm5120/dev/
admwdog.c 73 wdog0 = __SHIFTIN(sc->sc_smw.smw_period * 100, ADM5120_WDOG_WTS_MASK) |
95 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
96 smw->smw_period = 32;
97 else if (smw->smw_period > ADMWDOG_MAX_PERIOD)
126 smw->smw_period = ADMWDOG_MAX_PERIOD;
  /src/sys/arch/arm/gemini/
gemini_wdt.c 99 r = (sc->sc_smw.smw_period != 0) ?
100 WATCHDOG_COUNT(sc->sc_smw.smw_period) : WDT_WDLOAD_DFLT;
129 if (period != sc->sc_smw.smw_period) {
130 sc->sc_smw.smw_period = period;
175 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
176 sc->sc_smw.smw_period = WDT_WDLOAD_DFLT;
178 sc->sc_smw.smw_period = smw->smw_period;
179 geminiwdt_set_timeout(sc->sc_smw.smw_period);
  /src/sys/arch/arm/nvidia/
tegra_timer.c 118 sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT;
122 sc->sc_smw.smw_period);
138 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
139 sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT;
140 } else if (smw->smw_period == 0 || smw->smw_period > 1000) {
143 sc->sc_smw.smw_period = smw->smw_period;
145 u_int tval = (sc->sc_smw.smw_period * 1000000) / 2;
  /src/sys/arch/arm/amlogic/
meson_wdt.c 88 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
89 sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT;
90 } else if (smw->smw_period == 0 ||
91 smw->smw_period > WATCHDOG_PERIOD_MAX) {
94 sc->sc_wdog.smw_period = smw->smw_period;
97 const u_int tcnt = sc->sc_wdog.smw_period * WATCHDOG_TICKS_PER_SEC;
158 sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT;
mesongx_wdt.c 87 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
88 sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT;
89 } else if (smw->smw_period == 0 ||
90 smw->smw_period > WATCHDOG_PERIOD_MAX) {
93 sc->sc_wdog.smw_period = smw->smw_period;
100 WDT_WRITE(sc, WATCHDOG_TCNT, sc->sc_wdog.smw_period * 1000);
167 sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT;
  /src/sys/arch/arm/xscale/
i80321_wdog.c 93 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
94 smw->smw_period = sc->sc_wdog_period;
95 else if (smw->smw_period != sc->sc_wdog_period) {
138 sc->sc_smw.smw_period = sc->sc_wdog_period;
ixp425_wdog.c 127 sc->sc_smw.smw_period = IXPDOG_DEFAULT_PERIOD;
184 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
185 smw->smw_period = IXPDOG_DEFAULT_PERIOD;
186 sc->sc_preset = IXPDOG_COUNTS_PER_SEC * hz * smw->smw_period;
188 sc->sc_preset < smw->smw_period)
  /src/sys/arch/arm/sunxi/
sunxi_wdt.c 133 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
134 smw->smw_period = SUNXI_WDT_PERIOD_DEFAULT;
135 intv = sunxi_wdt_map_period(sc, smw->smw_period,
136 &sc->sc_smw.smw_period);
171 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
172 smw->smw_period = SUNXI_WDT_PERIOD_DEFAULT;
173 intv = sunxi_wdt_map_period(sc, smw->smw_period,
174 &sc->sc_smw.smw_period);
236 sc->sc_smw.smw_period = SUNXI_WDT_PERIOD_DEFAULT;
255 sc->sc_smw.smw_period);
    [all...]
  /src/sys/arch/arm/acpi/
sbsawdt_acpi.c 143 sc->sc_smw.smw_period = sc->sc_max_period;
148 sc->sc_smw.smw_period);
174 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
175 smw->smw_period = sc->sc_max_period;
176 else if (smw->smw_period > sc->sc_max_period)
185 const uint32_t wor = smw->smw_period * sc->sc_cntfreq / 2;
  /src/sys/arch/arm/imx/
imxwdog.c 103 if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) {
110 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
112 smw->smw_period = IMXWDOG_PERIOD_DEFAULT;
118 if (smw->smw_period >= sc->sc_wdog_max_period)
121 sc->sc_wdog_period = smw->smw_period;
171 sc->sc_smw.smw_period = sc->sc_wdog_period;
  /src/sys/dev/ic/
dwc_wdt.c 133 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
134 smw->smw_period = DWCWDT_PERIOD_DEFAULT;
136 intv = dwcwdt_map_period(sc, smw->smw_period,
137 &sc->sc_smw.smw_period);
162 sc->sc_smw.smw_period = DWCWDT_PERIOD_DEFAULT;
168 sc->sc_smw.smw_period);
  /src/sys/arch/powerpc/ibm4xx/dev/
wdog.c 106 sc->sc_smw.smw_period = sc->sc_wdog_period;
136 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
137 smw->smw_period = sc->sc_wdog_period;
138 else if (smw->smw_period != sc->sc_wdog_period) {
  /src/sys/dev/sysmon/
swwdog.c 165 sc->sc_smw.smw_period = SWDOG_DEFAULT;
217 if (smw->smw_period == 0)
219 else if (smw->smw_period == WDOG_PERIOD_DEFAULT)
220 sc->sc_smw.smw_period = SWDOG_DEFAULT;
222 sc->sc_smw.smw_period = smw->smw_period;
239 callout_schedule(&sc->sc_c, sc->sc_smw.smw_period * hz);
263 sc->sc_smw.smw_period);
sysmon_wdog.c 175 WDOG_MODE_DISARMED, smw->smw_period);
215 wm->wm_period = smw->smw_period;
257 wm->wm_period = smw->smw_period;
452 u_int operiod = smw->smw_period;
456 smw->smw_period = period;
485 smw->smw_period = operiod;
499 WDOG_PERIOD_TO_TICKS(smw->smw_period) / 2,
527 WDOG_PERIOD_TO_TICKS(smw->smw_period) / 2,
549 smw->smw_period))
  /src/sys/arch/mips/sibyte/dev/
sbwdog.c 111 sc->sc_smw.smw_period = sc->sc_wdog_period;
152 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
154 smw->smw_period = SBWDOG_DEFAULT_PERIOD; /* XXX needed?? */
155 } else if (smw->smw_period > 8) {
159 sc->sc_wdog_period = smw->smw_period;
  /src/sys/arch/powerpc/booke/dev/
e500wdog.c 112 && smw->smw_period == sc->sc_wdog_period) {
117 sc->sc_wdog_period, smw->smw_period);
118 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
120 smw->smw_period = PQ3WDOG_PERIOD_DEFAULT;
172 sc->sc_smw.smw_period = sc->sc_wdog_period;
  /src/sys/arch/arm/ti/
ti_wdt.c 163 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
164 sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT;
166 sc->sc_wdog.smw_period = smw->smw_period;
168 if (sc->sc_wdog.smw_period == 0)
171 counter_val = ~(sc->sc_wdog.smw_period * sc->sc_rate / 2);
253 sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT;
  /src/sys/arch/arm/nxp/
imxwdog.c 121 if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) {
128 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
130 smw->smw_period = IMXWDOG_PERIOD_DEFAULT;
136 if (smw->smw_period >= sc->sc_wdog_max_period)
139 sc->sc_wdog_period = smw->smw_period;
216 sc->sc_smw.smw_period = sc->sc_wdog_period;
  /src/sys/arch/i386/pci/
geodewdg.c 177 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
178 smw->smw_period = 32;
179 else if (smw->smw_period > SC1100_WDIVL_MAX) /* too big? */
182 GEODE_DPRINTF(("%s: period %u\n", __func__, smw->smw_period));
184 ticks = smw->smw_period * SC1100_WDCLK_HZ;
234 sc->sc_smw.smw_period = 32;
  /src/sys/dev/acpi/
acpi_wdrt.c 222 sc->sc_smw.smw_period = sc->sc_max_period;
272 __func__, smw->smw_mode, smw->smw_period));
285 if (smw->smw_period == 0)
287 if (smw->smw_period > sc->sc_max_period)
288 smw->smw_period = sc->sc_max_period;
320 __func__, smw->smw_mode, smw->smw_period));
323 val = smw->smw_period * sc->sc_period_scale;
  /src/sys/arch/arm/cortex/
a9wdt.c 148 if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) {
159 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
161 smw->smw_period = A9WDT_PERIOD_DEFAULT;
167 if (smw->smw_period >= sc->sc_wdog_max_period) {
247 sc->sc_smw.smw_period = sc->sc_wdog_period;
  /src/sys/arch/arm/samsung/
exynos_wdt.c 135 if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) {
148 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
150 smw->smw_period = EXYNOS_WDT_PERIOD_DEFAULT;
156 if (smw->smw_period * sc->sc_freq >= UINT16_MAX) {
272 sc->sc_smw.smw_period = sc->sc_wdog_period;
  /src/sys/arch/sparc64/dev/
pld_wdog.c 88 device_xname(sc->sc_dev), smw->smw_mode, smw->smw_period);
93 smw->smw_period * 10);
112 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
113 smw->smw_period = sc->sc_wdog_period;
200 sc->sc_smw.smw_period = sc->sc_wdog_period;
  /src/sys/arch/arm/broadcom/
bcm2835_pmwdog.c 152 sc->sc_smw.smw_period = BCM2835_PM_DEFAULT_PERIOD;
188 if (smw->smw_period == WDOG_PERIOD_DEFAULT)
189 smw->smw_period = BCM2835_PM_DEFAULT_PERIOD;
190 if (smw->smw_period > (BCM2835_PM_WDOG_TIMEMASK >> 16))
213 uint32_t timeout = smw->smw_period << 16;

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