| /src/external/apache2/llvm/dist/clang/lib/Headers/ |
| amxintrin.h | 136 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in src0 with
147 /// \param src0
151 #define _tile_dpbssd(dst, src0, src1) \
152 __builtin_ia32_tdpbssd((dst), (src0), (src1))
155 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in src0 with
166 /// \param src0
170 #define _tile_dpbsud(dst, src0, src1) \
171 __builtin_ia32_tdpbsud((dst), (src0), (src1))
174 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in src0 with
185 /// \param src0
[all...] |
| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| byteunpack.s | 8 .macro _bu_pre_test i0:req, src0:req, src1:req
10 imm32 R0, \src0
21 .macro bu_test i0:req, dst0:req, dst1:req, src0:req, src1:req
22 _bu_pre_test \i0, \src0, \src1
26 .macro bu_r_test i0:req, dst0:req, dst1:req, src0:req, src1:req
27 _bu_pre_test \i0, \src0, \src1
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| byteunpack.s | 8 .macro _bu_pre_test i0:req, src0:req, src1:req
10 imm32 R0, \src0
21 .macro bu_test i0:req, dst0:req, dst1:req, src0:req, src1:req
22 _bu_pre_test \i0, \src0, \src1
26 .macro bu_r_test i0:req, dst0:req, dst1:req, src0:req, src1:req
27 _bu_pre_test \i0, \src0, \src1
|
| /src/common/lib/libc/string/ |
| bcopy.c | 77 memcpy(void *dst0, const void *src0, size_t length)
80 memmove(void *dst0, const void *src0, size_t length)
83 bcopy(const void *src0, void *dst0, size_t length)
87 const char *src = src0;
133 _DIAGASSERT((unsigned long)src >= (unsigned long)src0);
|
| /src/tests/lib/libc/locale/ |
| t_iconv.c | 151 char *src0, *src, *dst0, *dst; local
161 src = src0 = inbuf + 1;
198 ATF_CHECK_MSG(src0 <= src && src <= src0 + srcleft0, "[%s] iconv:"
200 title, src0, src, src0, src0 + srcleft0);
322 char *src0, *src, *dst0, *dst; local
332 src = src0 = in;
346 ATF_CHECK_MSG(src0 <= src && src <= src0 + srcleft0, "[%s] iconv:
[all...] |
| /src/external/gpl3/binutils/dist/opcodes/ |
| bfin-dis.c | 559 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
564 s0 = dregs_hi (src0);
566 s0 = dregs_lo (src0);
580 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
606 decode_multfunc (h0, h1, src0, src1, outf);
1649 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1653 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); local
1656 if (opc == 5 && src1 == src0)
1660 OUTS (outf, pregs (src0));
1667 OUTS (outf, dregs (src0));
2948 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
3032 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
3083 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask); local
3889 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); local
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| bfin-dis.c | 559 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
564 s0 = dregs_hi (src0);
566 s0 = dregs_lo (src0);
580 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
606 decode_multfunc (h0, h1, src0, src1, outf);
1649 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1653 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); local
1656 if (opc == 5 && src1 == src0)
1660 OUTS (outf, pregs (src0));
1667 OUTS (outf, dregs (src0));
2948 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
3032 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
3083 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask); local
3889 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); local
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| bfin-dis.c | 559 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
564 s0 = dregs_hi (src0);
566 s0 = dregs_lo (src0);
580 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
606 decode_multfunc (h0, h1, src0, src1, outf);
1649 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1653 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); local
1656 if (opc == 5 && src1 == src0)
1660 OUTS (outf, pregs (src0));
1667 OUTS (outf, dregs (src0));
2948 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
3032 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
3083 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask); local
3889 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); local
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| bfin-dis.c | 559 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
564 s0 = dregs_hi (src0);
566 s0 = dregs_lo (src0);
580 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
606 decode_multfunc (h0, h1, src0, src1, outf);
1649 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1653 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); local
1656 if (opc == 5 && src1 == src0)
1660 OUTS (outf, pregs (src0));
1667 OUTS (outf, dregs (src0));
2948 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
3032 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
3083 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask); local
3889 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); local
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/bfin/ |
| bfin-sim.c | 1334 /* Perform a multiplication of D registers SRC0 and SRC1, sign- or
1339 decode_multfunc (SIM_CPU *cpu, int h0, int h1, int src0, int src1, int mmod,
1342 bu32 s0 = DREG (src0), s1 = DREG (src1);
1584 decode_macfunc (SIM_CPU *cpu, int which, int op, int h0, int h1, int src0,
1605 bu64 res = decode_multfunc (cpu, h0, h1, src0, src1, mmod,
2805 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
2809 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); local
2813 TRACE_EXTRACT (cpu, "%s: opc:%i dst:%i src1:%i src0:%i",
2814 __func__, opc, dst, src1, src0);
2821 TRACE_INSN (cpu, "R%i = R%i + R%i;", dst, src0, src1)
3802 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
3963 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
4068 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask); local
5232 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); local
[all...] |
| /src/external/gpl3/gdb/dist/sim/bfin/ |
| bfin-sim.c | 1334 /* Perform a multiplication of D registers SRC0 and SRC1, sign- or
1339 decode_multfunc (SIM_CPU *cpu, int h0, int h1, int src0, int src1, int mmod,
1342 bu32 s0 = DREG (src0), s1 = DREG (src1);
1584 decode_macfunc (SIM_CPU *cpu, int which, int op, int h0, int h1, int src0,
1605 bu64 res = decode_multfunc (cpu, h0, h1, src0, src1, mmod,
2805 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
2809 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); local
2813 TRACE_EXTRACT (cpu, "%s: opc:%i dst:%i src1:%i src0:%i",
2814 __func__, opc, dst, src1, src0);
2821 TRACE_INSN (cpu, "R%i = R%i + R%i;", dst, src0, src1)
3802 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
3963 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
4068 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask); local
5232 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); local
[all...] |
| /src/sys/arch/luna68k/dev/ |
| omrasops.c | 819 * src0: source pointer in Plane0.
820 * if y-forward, src0 > dst0, point to left-top.
821 * if y-backward, src0 < dst0, point to left-bottom.
828 om4_rascopy_multi(uint8_t *dst0, uint8_t *src0, int16_t width, int16_t height)
884 " move.l (%[src0]),(%[dst0])+ ;\n" /* P0 */
885 " adda.l %[PLANEOFFS],%[src0] ;\n"
886 " move.l (%[src0]),(%[dst1])+ ;\n" /* P1 */
887 " adda.l %[PLANEOFFS],%[src0] ;\n"
888 " move.l (%[src0]),(%[dst2])+ ;\n" /* P2 */
889 " adda.l %[PLANEOFFS],%[src0] ;\n
1206 uint8_t *src0 = src + OMFB_PLANEOFFS; local
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIPeepholeSDWA.cpp | 308 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) {
343 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
349 // If this is not src0 then it could be src1
537 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
538 auto Imm = foldToImm(*Src0);
577 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
578 auto Imm = foldToImm(*Src0);
645 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0)
[all...] |
| R600ExpandSpecialInstrs.cpp | 111 MI.getOperand(1).getReg(), // src0
146 Register Src0 =
147 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src0))
152 (void) Src0;
154 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
156 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
198 Register Src0 =
199 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::src0)).getReg();
211 Src0 = TRI.getSubReg(Src0, SubRegIndex)
[all...] |
| GCNDPPCombine.cpp | 8 // The pass combines V_MOV_B32_dpp instruction with its VALU uses as a DPP src0
238 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
239 assert(Src0);
240 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {
241 LLVM_DEBUG(dbgs() << " failed: src0 is illegal\n");
245 DPPInst.add(*Src0);
425 auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
540 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0);
[all...] |
| /src/crypto/external/apache2/openssl/dist/crypto/ec/asm/ |
| ecp_nistz256-x86_64.pl | 3062 my ($a,$b,$src0) = @_;
3063 my $bias = $src0 eq "%rax" ? 0 : -128;
3065 " mov $b, $src0
3075 my ($a,$src0) = @_;
3076 my $bias = $src0 eq "%rax" ? 0 : -128;
3078 " mov 8*0+$a, $src0
3225 my ($src0,$sfx,$bias);
3229 $src0 = "%rax";
3247 $src0 = "%rdx";
3297 mov 0x40+8*0($a_ptr), $src0
[all...] |
| /src/crypto/external/bsd/openssl/dist/crypto/ec/asm/ |
| ecp_nistz256-x86_64.pl | 3060 my ($a,$b,$src0) = @_;
3061 my $bias = $src0 eq "%rax" ? 0 : -128;
3063 " mov $b, $src0
3073 my ($a,$src0) = @_;
3074 my $bias = $src0 eq "%rax" ? 0 : -128;
3076 " mov 8*0+$a, $src0
3223 my ($src0,$sfx,$bias);
3227 $src0 = "%rax";
3245 $src0 = "%rdx";
3295 mov 0x40+8*0($a_ptr), $src0
[all...] |
| /src/crypto/external/bsd/openssl.old/dist/crypto/ec/asm/ |
| ecp_nistz256-x86_64.pl | 3058 my ($a,$b,$src0) = @_;
3059 my $bias = $src0 eq "%rax" ? 0 : -128;
3061 " mov $b, $src0
3071 my ($a,$src0) = @_;
3072 my $bias = $src0 eq "%rax" ? 0 : -128;
3074 " mov 8*0+$a, $src0
3221 my ($src0,$sfx,$bias);
3225 $src0 = "%rax";
3243 $src0 = "%rdx";
3293 mov 0x40+8*0($a_ptr), $src0
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| nouveau_nvkm_subdev_clk_gt215.c | 372 const u32 src0 = 0x004120 + (idx * 4); local
387 nvkm_mask(device, src0, 0x003f3141, 0x00000101 | info->clk);
396 nvkm_mask(device, src0, 0x00000101, 0x00000000);
407 disable_clk_src(clk, src0);
|
| nouveau_nvkm_subdev_clk_gf100.c | 283 u32 src0, div0, div1D, div1P = 0; local
291 clk0 = calc_src(clk, idx, freq, &src0, &div0);
305 info->dsrc = src0;
|
| nouveau_nvkm_subdev_clk_gk104.c | 297 u32 src0, div0, div1D, div1P = 0; local
305 clk0 = calc_src(clk, idx, freq, &src0, &div0);
319 info->dsrc = src0;
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-bfin.c | 1159 REG_T dst, REG_T src0, REG_T src1, int w0)
1183 ASSIGN_R (src0);
1192 REG_T dst, REG_T src0, REG_T src1, int w0)
1214 ASSIGN_R (src0);
1222 REG_T dst0, REG_T dst1, REG_T src0, REG_T src1)
1233 ASSIGN_R (src0);
1240 bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0,
1250 ASSIGN_R (src0);
1641 bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc)
1645 ASSIGN_R (src0);
2475 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); local
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-bfin.c | 1159 REG_T dst, REG_T src0, REG_T src1, int w0)
1183 ASSIGN_R (src0);
1192 REG_T dst, REG_T src0, REG_T src1, int w0)
1214 ASSIGN_R (src0);
1222 REG_T dst0, REG_T dst1, REG_T src0, REG_T src1)
1233 ASSIGN_R (src0);
1240 bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0,
1250 ASSIGN_R (src0);
1641 bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc)
1645 ASSIGN_R (src0);
2475 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); local
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/fr30/ |
| fr30.cc | 945 rtx src0;
950 src0 = operand_subword (src, 0, TRUE, mode);
953 emit_move_insn (adjust_address (dest, SImode, 0), src0);
943 rtx src0; local
951 emit_move_insn (adjust_address (dest, SImode, 0), src0); local
|
| /src/external/gpl3/gcc.old/dist/gcc/config/fr30/ |
| fr30.cc | 942 rtx src0;
947 src0 = operand_subword (src, 0, TRUE, mode);
950 emit_move_insn (adjust_address (dest, SImode, 0), src0);
940 rtx src0; local
948 emit_move_insn (adjust_address (dest, SImode, 0), src0); local
|
