| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dwb.c | 84 CNV_SOURCE_HEIGHT, params->cnv_params.src_height);
110 (params->cnv_params.src_height != params->dest_height)) {
170 (params->cnv_params.src_height != params->dest_height)) {
300 dwb_program_vert_scalar(dwbc20, params->cnv_params.src_height,
|
| amdgpu_dcn20_dwb_scl.c | 803 uint32_t src_height,
826 src_height, dest_height);
|
| dcn20_dwb.h | 447 uint32_t src_height,
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_overlay.c | 824 sheight = params->src_height;
834 sheight |= (params->src_height / uv_vscale) << 16;
977 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
981 if (rec->src_height > IMAGE_MAX_HEIGHT ||
987 if (rec->src_height < N_VERT_Y_TAPS*4 ||
1051 tmp = rec->stride_Y*rec->src_height;
1062 tmp = rec->stride_Y * rec->src_height;
1066 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1155 if (params->src_scan_height > params->src_height ||
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services_types.h | 129 uint32_t src_height; member in struct:dm_pp_single_disp_config
|
| dc_types.h | 488 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ member in struct:dc_dwb_cnv_params
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| amdgpu_dce110_clk_mgr.c | 154 cfg->src_height = stream->src.height;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| dce_calcs.h | 396 struct bw_fixed src_height[maximum_number_of_surfaces]; member in struct:bw_calcs_data
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dce_calcs.c | 395 data->src_height[maximum_number_of_surfaces - 2] = data->src_height[5];
396 data->src_height[maximum_number_of_surfaces - 1] = data->src_height[5];
432 data->src_height_after_surface_type = bw_div(data->src_height[i], bw_int_to_fixed(2));
439 data->src_height_after_surface_type = data->src_height[i];
1435 data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
1439 data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->mcifwr_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
1997 data->v_blank_nbp_state_dram_speed_change_latency_supported = bw_min2(data->v_blank_nbp_state_dram_speed_change_latency_supported, bw_add(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[i], bw_sub(bw_div(data->src_height[i], data->v_scale_ratio[i]), bw_int_to_fixed(4)))), data->h_total[i]), data->pixel_rate[i]), data->nbp_state_change_watermark[i]), vbios->nbp_state_change_latency));
2806 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height)
[all...] |
| calcs_logger.h | 430 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_height[%d]:%d", i, bw_fixed_to_int(data->src_height[i]));
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_clk_mgr.c | 526 cfg->src_height = stream->src.height;
|
| /src/sys/external/bsd/drm2/dist/include/uapi/drm/ |
| i915_drm.h | 1449 __u16 src_height; member in struct:drm_intel_overlay_put_image
|
