| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| dce110_timing_generator.h | 119 #define DCE110TG_FROM_TG(tg)\
120 container_of(tg, struct dce110_timing_generator, base)
123 struct dce110_timing_generator *tg,
128 /* determine if given timing can be supported by TG */
130 struct timing_generator *tg,
138 struct timing_generator *tg,
142 bool dce110_timing_generator_enable_crtc(struct timing_generator *tg);
143 bool dce110_timing_generator_disable_crtc(struct timing_generator *tg);
146 struct timing_generator *tg,
149 /**************** TG current status ******************
[all...] |
| amdgpu_dce110_timing_generator_v.c | 47 tg->ctx->logger
58 static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg)
70 dm_write_reg(tg->ctx,
75 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value);
80 dm_write_reg(tg->ctx,
86 static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg)
90 value = dm_read_reg(tg->ctx,
96 dm_write_reg(tg->ctx,
100 * tg->funcs->disable_stereo(tg);
[all...] |
| amdgpu_dce110_timing_generator.c | 71 struct timing_generator *tg,
97 struct timing_generator *tg)
102 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
105 value = dm_read_reg(tg->ctx, addr);
111 struct timing_generator *tg,
115 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
118 regval = dm_read_reg(tg->ctx, address);
121 dm_write_reg(tg->ctx, address, regval);
128 bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
132 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
[all...] |
| amdgpu_dce110_hw_sequencer.c | 667 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dce110_enable_stream
690 tg->funcs->set_early_control(tg, early_control);
1185 pipe_ctx->stream_res.tg->inst + 1);
1197 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
1252 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1261 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1262 pipe_ctx->stream_res.tg,
1285 pipe_ctx->stream_res.tg->funcs->set_blank_color
1499 struct timing_generator *tg; local in function:disable_vga_and_power_gate_all_controllers
2398 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:init_hw
[all...] |
| amdgpu_dce110_resource.c | 873 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1113 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];
1128 pipe_ctx->stream_res.tg->inst,
1136 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
1145 pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
1146 pipe_ctx->stream_res.tg,
1158 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1159 pipe_ctx->stream_res.tg,
1419 dm_error("DC: failed to create tg!\n")
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| timing_generator.h | 139 bool (*validate_timing)(struct timing_generator *tg,
141 void (*program_timing)(struct timing_generator *tg,
161 bool (*enable_crtc)(struct timing_generator *tg);
162 bool (*disable_crtc)(struct timing_generator *tg);
163 bool (*is_counter_moving)(struct timing_generator *tg);
164 void (*get_position)(struct timing_generator *tg,
167 uint32_t (*get_frame_count)(struct timing_generator *tg);
169 struct timing_generator *tg,
177 bool (*is_matching_timing)(struct timing_generator *tg,
179 void (*set_early_control)(struct timing_generator *tg,
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| dce80_timing_generator.h | 36 struct dce110_timing_generator *tg,
|
| amdgpu_dce80_timing_generator.c | 92 static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)
96 + DCE110TG_FROM_TG(tg)->offsets.dmif;
97 uint32_t value = dm_read_reg(tg->ctx, addr);
110 dm_write_reg(tg->ctx, addr, value);
113 static void program_timing(struct timing_generator *tg,
123 program_pix_dur(tg, timing->pix_clk_100hz);
125 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios);
129 struct timing_generator *tg,
133 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
135 uint32_t value = dm_read_reg(tg->ctx, addr)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_timing_generator.c | 91 struct timing_generator *tg)
94 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
96 tg->ctx,
105 /* determine if given timing can be supported by TG */
107 struct timing_generator *tg,
116 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
119 tg,
133 bool dce120_tg_validate_timing(struct timing_generator *tg,
136 return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE);
141 bool dce120_timing_generator_enable_crtc(struct timing_generator *tg)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_hwseq.c | 61 if (lock && pipe->stream_res.tg->funcs->is_blanked &&
62 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
65 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
81 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
87 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);
88 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);
|
| dmub_psr.c | 158 if (pipe_ctx->stream_res.tg)
159 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hwseq.c | 165 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
166 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
167 pipe_ctx->stream_res.tg->funcs->set_gsl(
168 pipe_ctx->stream_res.tg,
171 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
172 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);
278 struct timing_generator *tg)
293 tg->funcs->get_otg_active_size(tg,
298 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1)
2000 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dcn20_setup_vupdate_interrupt
2225 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dcn20_enable_stream
2320 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn20_fpga_init_hw
2327 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn20_fpga_init_hw
2351 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn20_fpga_init_hw
2382 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn20_fpga_init_hw
2398 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn20_fpga_init_hw
[all...] |
| dcn20_hwseq.h | 88 struct timing_generator *tg);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer.c | 95 struct timing_generator *tg; local in function:dcn10_lock_all_pipes
100 tg = pipe_ctx->stream_res.tg;
102 * Only lock the top pipe's tg to prevent redundant
107 !tg->funcs->is_tg_enabled(tg))
111 tg->funcs->lock(tg);
113 tg->funcs->unlock(tg);
346 struct timing_generator *tg = pool->timing_generators[i]; local in function:dcn10_log_hw_state
469 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dcn10_did_underflow_occur
1146 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn10_init_pipes
1184 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn10_init_pipes
2518 struct timing_generator *tg; local in function:dcn10_apply_ctx_for_surface
2890 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dcn10_update_pending_status
3201 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dcn10_setup_periodic_interrupt
3220 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dcn10_setup_vupdate_interrupt
[all...] |
| amdgpu_dcn10_hw_sequencer_debug.c | 432 struct timing_generator *tg = pool->timing_generators[i]; local in function:dcn10_get_otg_states
436 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
444 tg->inst,
499 struct timing_generator *tg = pool->timing_generators[i]; local in function:dcn10_clear_otpc_underflow
502 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
505 tg->funcs->clear_optc_underflow(tg);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/ |
| amdgpu_irq_service_dce110.c | 219 struct timing_generator *tg = local in function:dce110_vblank_set
220 dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
223 if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {
|
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_connector.c | 2321 struct drm_tile_group *tg = container_of(kref, struct drm_tile_group, refcount); local in function:drm_tile_group_free
2322 struct drm_device *dev = tg->dev;
2324 idr_remove(&dev->mode_config.tile_idr, tg->id);
2326 kfree(tg);
2332 * @tg: tile group to drop reference to.
2337 struct drm_tile_group *tg)
2339 kref_put(&tg->refcount, drm_tile_group_free);
2356 struct drm_tile_group *tg; local in function:drm_mode_get_tile_group
2359 idr_for_each_entry(&dev->mode_config.tile_idr, tg, id) {
2360 if (!memcmp(tg->group_data, topology, 8))
2386 struct drm_tile_group *tg; local in function:drm_mode_create_tile_group
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_hw_sequencer.c | 278 struct timing_generator *tg)
283 if (!tg->funcs->is_blanked)
286 if (tg->funcs->is_blanked(tg))
|
| amdgpu_dc_stream.c | 516 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; local in function:dc_stream_get_vblank_counter
521 return tg->funcs->get_frame_count(tg);
575 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; local in function:dc_stream_get_scanoutpos
580 tg->funcs->get_scanoutpos(tg,
|
| amdgpu_dc.c | 294 if (pipe->stream == stream && pipe->stream_res.tg) {
350 struct timing_generator *tg; local in function:dc_stream_configure_crc
376 tg = pipe->stream_res.tg;
379 if (tg->funcs->configure_crc)
380 return tg->funcs->configure_crc(tg, ¶m);
399 struct timing_generator *tg; local in function:dc_stream_get_crc
410 tg = pipe->stream_res.tg;
1049 struct timing_generator *tg; local in function:dc_validate_seamless_boot_timing
[all...] |
| amdgpu_dc_debug.c | 331 pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);
342 pipe_ctx->stream_res.tg->inst,
|
| amdgpu_dc_link_hwss.c | 467 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
469 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
475 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
476 pipe_ctx->stream_res.tg,
|
| /src/sbin/routed/ |
| parms.c | 592 struct tgate *tg; local in function:parse_parms
822 tg = (struct tgate *)rtmalloc(sizeof(*tg),
825 memset(tg, 0, sizeof(*tg));
826 tg->tgate_addr = addr;
834 || !getnet(buf2, &tg->tgate_nets[i].net,
835 &tg->tgate_nets[i].mask)
836 || tg->tgate_nets[i].net == RIP_DEFAULT
837 || tg->tgate_nets[i].mask == 0)
[all...] |
| input.c | 155 struct tgate *tg = 0; local in function:input
582 tg = tgates;
583 while (tg->tgate_addr != FROM_NADDR) {
584 tg = tg->tgate_next;
585 if (tg == 0) {
685 if (tg && (tn = tg->tgate_nets)->mask != 0) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| hw_sequencer.h | 199 struct timing_generator *tg);
|
