| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_debug.c | 142 "plane_state->tiling_info.gfx8.tile_split = %d;\n"
153 plane_state->tiling_info.gfx8.tile_split,
234 "plane_info->tiling_info.gfx8.tile_split = %d;\n"
245 update->plane_info->tiling_info.gfx8.tile_split,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_hw_types.h | 317 * For color render targets, TILE_SPLIT >= 256B.
319 enum tile_split_values tile_split; member in struct:dc_tiling_info::__anon788fbb990708
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_evergreen_cs.c | 1212 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_cs_handle_reg
1216 &tile_split);
1218 ib[idx] |= DB_TILE_SPLIT(tile_split) |
1476 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_cs_handle_reg
1480 &tile_split);
1482 ib[idx] |= CB_TILE_SPLIT(tile_split) |
1504 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_cs_handle_reg
1508 &tile_split);
1510 ib[idx] |= CB_TILE_SPLIT(tile_split) |
2393 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_packet3_check
[all...] |
| radeon_atombios_crtc.c | 1161 unsigned bankw, bankh, mtaspect, tile_split; local in function:dce4_crtc_do_set_base
1283 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1293 tile_split_bytes = 64 << tile_split;
1303 tile_split);
1348 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
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| radeon_evergreen.c | 1121 unsigned *tile_split)
1126 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
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| radeon.h | 370 unsigned *tile_split);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_mem_input.c | 383 GRPH_TILE_SPLIT, info->gfx8.tile_split,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_mem_input_v.c | 189 set_reg_field_value(value, info->gfx8.tile_split,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 1994 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v10_0_crtc_do_set_base
1999 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2006 tile_split);
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| amdgpu_dce_v11_0.c | 2036 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v11_0_crtc_do_set_base
2041 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2048 tile_split);
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| amdgpu_dce_v6_0.c | 1943 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v6_0_crtc_do_set_base
1948 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1953 fb_format |= GRPH_TILE_SPLIT(tile_split);
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| amdgpu_dce_v8_0.c | 1915 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v8_0_crtc_do_set_base
1920 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1925 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm.c | 3263 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; local in function:fill_plane_buffer_attributes
3268 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
3275 tiling_info->gfx8.tile_split = tile_split;
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