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    Searched refs:tiling_flags (Results 1 - 25 of 27) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_object.c 609 lobj->tiling_flags = bo->tiling_flags;
614 lobj->tiling_flags = lobj->robj->tiling_flags;
630 if (!bo->tiling_flags)
669 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
691 uint32_t tiling_flags, uint32_t pitch)
699 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
700 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
701 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
    [all...]
radeon_fb.c 147 u32 tiling_flags = 0; local in function:radeonfb_create_pinned_object
174 tiling_flags = RADEON_TILING_MACRO;
179 tiling_flags |= RADEON_TILING_SWAP_32BIT;
182 tiling_flags |= RADEON_TILING_SWAP_16BIT;
188 if (tiling_flags) {
190 tiling_flags | RADEON_TILING_SURFACE,
radeon_object.h 149 u32 tiling_flags, u32 pitch);
151 u32 *tiling_flags, u32 *pitch);
radeon_r200.c 226 if (reloc->tiling_flags & RADEON_TILING_MACRO)
228 if (reloc->tiling_flags & RADEON_TILING_MICRO)
298 if (reloc->tiling_flags & RADEON_TILING_MACRO)
300 if (reloc->tiling_flags & RADEON_TILING_MICRO)
radeon_r300.c 752 if (reloc->tiling_flags & RADEON_TILING_MACRO)
754 if (reloc->tiling_flags & RADEON_TILING_MICRO)
756 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
821 if (reloc->tiling_flags & RADEON_TILING_MACRO)
823 if (reloc->tiling_flags & RADEON_TILING_MICRO)
825 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
906 if (reloc->tiling_flags & RADEON_TILING_MACRO)
908 if (reloc->tiling_flags & RADEON_TILING_MICRO)
910 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
radeon_legacy_crtc.c 391 uint32_t tiling_flags; local in function:radeon_crtc_do_set_base
438 tiling_flags = 0;
479 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
482 if (tiling_flags & RADEON_TILING_MICRO)
499 if (tiling_flags & RADEON_TILING_MACRO) {
515 if (tiling_flags & RADEON_TILING_MACRO) {
radeon_atombios_crtc.c 1160 uint32_t fb_format, fb_pitch_pixels, tiling_flags; local in function:dce4_crtc_do_set_base
1188 tiling_flags = 0;
1198 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1282 if (tiling_flags & RADEON_TILING_MACRO) {
1283 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1356 } else if (tiling_flags & RADEON_TILING_MICRO)
1483 uint32_t fb_format, fb_pitch_pixels, tiling_flags; local in function:avivo_crtc_do_set_base
1510 tiling_flags = 0;
1520 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1597 if (tiling_flags & RADEON_TILING_MACRO
    [all...]
radeon_evergreen_cs.c 102 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
104 if (tiling_flags & RADEON_TILING_MACRO)
106 else if (tiling_flags & RADEON_TILING_MICRO)
1209 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1210 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1211 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1214 evergreen_tiling_fields(reloc->tiling_flags,
1395 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1396 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1413 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
    [all...]
radeon_r100.c 1302 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1304 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1644 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1646 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1725 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1727 if (reloc->tiling_flags & RADEON_TILING_MICRO)
3113 uint32_t tiling_flags, uint32_t pitch,
3120 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3123 if (tiling_flags & RADEON_TILING_MACRO)
3126 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)
    [all...]
radeon_r600_cs.c 1047 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1146 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1149 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1477 u32 tiling_flags)
1499 if (tiling_flags & RADEON_TILING_MACRO)
1501 else if (tiling_flags & RADEON_TILING_MICRO)
1970 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1972 else if (reloc->tiling_flags & RADEON_TILING_MICRO)
1988 reloc->tiling_flags);
radeon_gem.c 534 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch);
555 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch);
radeon_vm.c 153 list[0].tiling_flags = 0;
165 list[idx].tiling_flags = 0;
radeon_display.c 498 uint32_t tiling_flags, pitch_pixels; local in function:radeon_crtc_page_flip_target
544 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
552 if (tiling_flags & RADEON_TILING_MACRO) {
radeon_asic.h 93 uint32_t tiling_flags, uint32_t pitch,
341 uint32_t tiling_flags, uint32_t pitch,
radeon.h 368 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
483 uint32_t tiling_flags; member in struct:radeon_bo_list
515 u32 tiling_flags; member in struct:radeon_bo
1982 uint32_t tiling_flags, uint32_t pitch,
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_fb.c 144 u32 tiling_flags = 0, domain; local in function:amdgpufb_create_pinned_object
173 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
179 if (tiling_flags) {
181 tiling_flags);
amdgpu_object.h 95 u64 tiling_flags; member in struct:amdgpu_bo
270 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
271 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
amdgpu_object.c 1152 * @tiling_flags: new flags
1160 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
1165 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
1168 bo->tiling_flags = tiling_flags;
1175 * @tiling_flags: returned flags
1180 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
1184 if (tiling_flags)
1185 *tiling_flags = bo->tiling_flags;
    [all...]
amdgpu_dce_v10_0.c 1862 uint64_t fb_location, tiling_flags; local in function:dce_v10_0_crtc_do_set_base
1900 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1903 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1997 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1998 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1999 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2000 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1)
    [all...]
amdgpu_dce_v11_0.c 1904 uint64_t fb_location, tiling_flags; local in function:dce_v11_0_crtc_do_set_base
1942 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1945 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2035 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2038 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2039 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2040 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2041 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2042 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2055 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1)
    [all...]
amdgpu_dce_v6_0.c 1822 uint64_t fb_location, tiling_flags; local in function:dce_v6_0_crtc_do_set_base
1859 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1942 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1945 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1946 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1947 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1948 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1949 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1957 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1961 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG)
    [all...]
amdgpu_dce_v8_0.c 1791 uint64_t fb_location, tiling_flags; local in function:dce_v8_0_crtc_do_set_base
1829 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1832 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1914 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1917 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1918 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1919 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1920 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1921 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1930 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1)
    [all...]
amdgpu_display.c 166 u64 tiling_flags; local in function:amdgpu_display_crtc_page_flip_target
221 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm.c 3113 uint64_t *tiling_flags)
3125 if (tiling_flags)
3126 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
3133 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
3135 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
3206 const uint64_t tiling_flags,
3262 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
3265 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
3266 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
3267 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT)
3508 uint64_t tiling_flags; local in function:fill_dc_plane_attributes
5109 uint64_t tiling_flags; local in function:dm_plane_helper_prepare_fb
6351 uint64_t tiling_flags; local in function:amdgpu_dm_commit_planes
7823 uint64_t tiling_flags; local in function:dm_determine_update_type_for_commit
    [all...]
  /src/sys/external/bsd/drm2/dist/include/uapi/drm/
radeon_drm.h 860 __u32 tiling_flags; member in struct:drm_radeon_gem_set_tiling
866 __u32 tiling_flags; member in struct:drm_radeon_gem_get_tiling

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