1 /* $NetBSD: if_mvgbe.c,v 1.70 2025/10/04 04:44:20 thorpej Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.70 2025/10/04 04:44:20 thorpej Exp $"); 29 30 #include "opt_multiprocessor.h" 31 32 #if defined MULTIPROCESSOR 33 #warning Queue Management Method 'Counters' not support. Please use mvxpe instead of this. 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/callout.h> 39 #include <sys/device.h> 40 #include <sys/endian.h> 41 #include <sys/errno.h> 42 #include <sys/evcnt.h> 43 #include <sys/kernel.h> 44 #include <sys/kmem.h> 45 #include <sys/mutex.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 #include <dev/marvell/mvgbereg.h> 52 53 #include <net/if.h> 54 #include <net/if_ether.h> 55 #include <net/if_media.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/ip.h> 60 61 #include <net/bpf.h> 62 #include <sys/rndsource.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include "locators.h" 68 69 /* #define MVGBE_DEBUG 3 */ 70 #ifdef MVGBE_DEBUG 71 #define DPRINTF(x) if (mvgbe_debug) printf x 72 #define DPRINTFN(n, x) if (mvgbe_debug >= (n)) printf x 73 int mvgbe_debug = MVGBE_DEBUG; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n, x) 77 #endif 78 79 80 #define MVGBE_READ(sc, reg) \ 81 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 82 #define MVGBE_WRITE(sc, reg, val) \ 83 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 84 #define MVGBE_READ_FILTER(sc, reg, val, c) \ 85 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 86 #define MVGBE_WRITE_FILTER(sc, reg, val, c) \ 87 bus_space_write_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 88 89 #define MVGBE_LINKUP_READ(sc) \ 90 bus_space_read_4((sc)->sc_iot, (sc)->sc_linkup.ioh, 0) 91 #define MVGBE_IS_LINKUP(sc) (MVGBE_LINKUP_READ(sc) & (sc)->sc_linkup.bit) 92 93 #define MVGBE_TX_RING_CNT 256 94 #define MVGBE_TX_RING_MSK (MVGBE_TX_RING_CNT - 1) 95 #define MVGBE_TX_RING_NEXT(x) (((x) + 1) & MVGBE_TX_RING_MSK) 96 #define MVGBE_RX_RING_CNT 256 97 #define MVGBE_RX_RING_MSK (MVGBE_RX_RING_CNT - 1) 98 #define MVGBE_RX_RING_NEXT(x) (((x) + 1) & MVGBE_RX_RING_MSK) 99 100 CTASSERT(MVGBE_TX_RING_CNT > 1 && MVGBE_TX_RING_NEXT(MVGBE_TX_RING_CNT) == 101 (MVGBE_TX_RING_CNT + 1) % MVGBE_TX_RING_CNT); 102 CTASSERT(MVGBE_RX_RING_CNT > 1 && MVGBE_RX_RING_NEXT(MVGBE_RX_RING_CNT) == 103 (MVGBE_RX_RING_CNT + 1) % MVGBE_RX_RING_CNT); 104 105 #define MVGBE_JSLOTS 384 /* XXXX */ 106 #define MVGBE_JLEN \ 107 ((MVGBE_MRU + MVGBE_HWHEADER_SIZE + MVGBE_RXBUF_ALIGN - 1) & \ 108 ~MVGBE_RXBUF_MASK) 109 #define MVGBE_NTXSEG 30 110 #define MVGBE_JPAGESZ PAGE_SIZE 111 #define MVGBE_RESID \ 112 (MVGBE_JPAGESZ - (MVGBE_JLEN * MVGBE_JSLOTS) % MVGBE_JPAGESZ) 113 #define MVGBE_JMEM \ 114 ((MVGBE_JLEN * MVGBE_JSLOTS) + MVGBE_RESID) 115 116 #define MVGBE_TX_RING_ADDR(sc, i) \ 117 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 118 offsetof(struct mvgbe_ring_data, mvgbe_tx_ring[(i)])) 119 120 #define MVGBE_RX_RING_ADDR(sc, i) \ 121 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 122 offsetof(struct mvgbe_ring_data, mvgbe_rx_ring[(i)])) 123 124 #define MVGBE_CDOFF(x) offsetof(struct mvgbe_ring_data, x) 125 #define MVGBE_CDTXOFF(x) MVGBE_CDOFF(mvgbe_tx_ring[(x)]) 126 #define MVGBE_CDRXOFF(x) MVGBE_CDOFF(mvgbe_rx_ring[(x)]) 127 128 #define MVGBE_CDTXSYNC(sc, x, n, ops) \ 129 do { \ 130 int __x, __n; \ 131 const int __descsize = sizeof(struct mvgbe_tx_desc); \ 132 \ 133 __x = (x); \ 134 __n = (n); \ 135 \ 136 /* If it will wrap around, sync to the end of the ring. */ \ 137 if ((__x + __n) > MVGBE_TX_RING_CNT) { \ 138 bus_dmamap_sync((sc)->sc_dmat, \ 139 (sc)->sc_ring_map, MVGBE_CDTXOFF(__x), \ 140 __descsize * (MVGBE_TX_RING_CNT - __x), (ops)); \ 141 __n -= (MVGBE_TX_RING_CNT - __x); \ 142 __x = 0; \ 143 } \ 144 \ 145 /* Now sync whatever is left. */ \ 146 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 147 MVGBE_CDTXOFF((__x)), __descsize * __n, (ops)); \ 148 } while (0 /*CONSTCOND*/) 149 150 #define MVGBE_CDRXSYNC(sc, x, ops) \ 151 do { \ 152 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 153 MVGBE_CDRXOFF((x)), sizeof(struct mvgbe_rx_desc), (ops)); \ 154 } while (/*CONSTCOND*/0) 155 156 #define MVGBE_IPGINTTX_DEFAULT 768 157 #define MVGBE_IPGINTRX_DEFAULT 768 158 159 #ifdef MVGBE_EVENT_COUNTERS 160 #define MVGBE_EVCNT_INCR(ev) (ev)->ev_count++ 161 #define MVGBE_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 162 #else 163 #define MVGBE_EVCNT_INCR(ev) /* nothing */ 164 #define MVGBE_EVCNT_ADD(ev, val) /* nothing */ 165 #endif 166 167 struct mvgbe_jpool_entry { 168 int slot; 169 LIST_ENTRY(mvgbe_jpool_entry) jpool_entries; 170 }; 171 172 struct mvgbe_chain { 173 void *mvgbe_desc; 174 struct mbuf *mvgbe_mbuf; 175 struct mvgbe_chain *mvgbe_next; 176 }; 177 178 struct mvgbe_txmap_entry { 179 bus_dmamap_t dmamap; 180 SIMPLEQ_ENTRY(mvgbe_txmap_entry) link; 181 }; 182 183 struct mvgbe_chain_data { 184 struct mvgbe_chain mvgbe_tx_chain[MVGBE_TX_RING_CNT]; 185 struct mvgbe_txmap_entry *mvgbe_tx_map[MVGBE_TX_RING_CNT]; 186 int mvgbe_tx_prod; 187 int mvgbe_tx_cons; 188 int mvgbe_tx_cnt; 189 190 struct mvgbe_chain mvgbe_rx_chain[MVGBE_RX_RING_CNT]; 191 bus_dmamap_t mvgbe_rx_map[MVGBE_RX_RING_CNT]; 192 bus_dmamap_t mvgbe_rx_jumbo_map; 193 int mvgbe_rx_prod; 194 int mvgbe_rx_cons; 195 int mvgbe_rx_cnt; 196 197 /* Stick the jumbo mem management stuff here too. */ 198 void *mvgbe_jslots[MVGBE_JSLOTS]; 199 void *mvgbe_jumbo_buf; 200 }; 201 202 struct mvgbe_ring_data { 203 struct mvgbe_tx_desc mvgbe_tx_ring[MVGBE_TX_RING_CNT]; 204 struct mvgbe_rx_desc mvgbe_rx_ring[MVGBE_RX_RING_CNT]; 205 }; 206 207 struct mvgbec_softc { 208 device_t sc_dev; 209 210 bus_space_tag_t sc_iot; 211 bus_space_handle_t sc_ioh; 212 213 kmutex_t sc_mtx; 214 215 int sc_flags; 216 }; 217 218 struct mvgbe_softc { 219 device_t sc_dev; 220 int sc_port; 221 uint32_t sc_version; 222 223 bus_space_tag_t sc_iot; 224 bus_space_handle_t sc_ioh; 225 bus_space_handle_t sc_dafh; /* dest address filter handle */ 226 bus_dma_tag_t sc_dmat; 227 228 struct ethercom sc_ethercom; 229 struct mii_data sc_mii; 230 uint8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */ 231 232 callout_t sc_tick_ch; /* tick callout */ 233 234 struct mvgbe_chain_data sc_cdata; 235 struct mvgbe_ring_data *sc_rdata; 236 bus_dmamap_t sc_ring_map; 237 u_short sc_if_flags; 238 unsigned int sc_ipginttx; 239 unsigned int sc_ipgintrx; 240 int sc_wdogsoft; 241 242 LIST_HEAD(__mvgbe_jfreehead, mvgbe_jpool_entry) sc_jfree_listhead; 243 LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead; 244 SIMPLEQ_HEAD(__mvgbe_txmaphead, mvgbe_txmap_entry) sc_txmap_head; 245 246 struct { 247 bus_space_handle_t ioh; 248 uint32_t bit; 249 } sc_linkup; 250 uint32_t sc_cmdsts_opts; 251 252 krndsource_t sc_rnd_source; 253 struct sysctllog *mvgbe_clog; 254 #ifdef MVGBE_EVENT_COUNTERS 255 struct evcnt sc_ev_rxoverrun; 256 struct evcnt sc_ev_wdogsoft; 257 #endif 258 }; 259 260 261 /* Gigabit Ethernet Unit Global part functions */ 262 263 static int mvgbec_match(device_t, struct cfdata *, void *); 264 static void mvgbec_attach(device_t, device_t, void *); 265 266 static int mvgbec_print(void *, const char *); 267 static int mvgbec_search(device_t, cfdata_t, const int *, void *); 268 269 /* MII functions */ 270 static int mvgbec_miibus_readreg(device_t, int, int, uint16_t *); 271 static int mvgbec_miibus_writereg(device_t, int, int, uint16_t); 272 static void mvgbec_miibus_statchg(struct ifnet *); 273 274 static void mvgbec_wininit(struct mvgbec_softc *, enum marvell_tags *); 275 276 /* Gigabit Ethernet Port part functions */ 277 278 static int mvgbe_match(device_t, struct cfdata *, void *); 279 static void mvgbe_attach(device_t, device_t, void *); 280 281 static void mvgbe_tick(void *); 282 static int mvgbe_intr(void *); 283 284 static void mvgbe_start(struct ifnet *); 285 static int mvgbe_ioctl(struct ifnet *, u_long, void *); 286 static int mvgbe_init(struct ifnet *); 287 static void mvgbe_stop(struct ifnet *, int); 288 static void mvgbe_watchdog(struct ifnet *); 289 290 static int mvgbe_ifflags_cb(struct ethercom *); 291 292 static int mvgbe_mediachange(struct ifnet *); 293 static void mvgbe_mediastatus(struct ifnet *, struct ifmediareq *); 294 295 static int mvgbe_init_rx_ring(struct mvgbe_softc *); 296 static int mvgbe_init_tx_ring(struct mvgbe_softc *); 297 static int mvgbe_newbuf(struct mvgbe_softc *, int, struct mbuf *, bus_dmamap_t); 298 static int mvgbe_alloc_jumbo_mem(struct mvgbe_softc *); 299 static void *mvgbe_jalloc(struct mvgbe_softc *); 300 static void mvgbe_jfree(struct mbuf *, void *, size_t, void *); 301 static int mvgbe_encap(struct mvgbe_softc *, struct mbuf *, uint32_t *); 302 static void mvgbe_rxeof(struct mvgbe_softc *); 303 static void mvgbe_txeof(struct mvgbe_softc *); 304 static uint8_t mvgbe_crc8(const uint8_t *, size_t); 305 static void mvgbe_filter_setup(struct mvgbe_softc *); 306 #ifdef MVGBE_DEBUG 307 static void mvgbe_dump_txdesc(struct mvgbe_tx_desc *, int); 308 #endif 309 static int mvgbe_ipginttx(struct mvgbec_softc *, struct mvgbe_softc *, 310 unsigned int); 311 static int mvgbe_ipgintrx(struct mvgbec_softc *, struct mvgbe_softc *, 312 unsigned int); 313 static void sysctl_mvgbe_init(struct mvgbe_softc *); 314 static int mvgbe_sysctl_ipginttx(SYSCTLFN_PROTO); 315 static int mvgbe_sysctl_ipgintrx(SYSCTLFN_PROTO); 316 317 CFATTACH_DECL_NEW(mvgbec_gt, sizeof(struct mvgbec_softc), 318 mvgbec_match, mvgbec_attach, NULL, NULL); 319 CFATTACH_DECL_NEW(mvgbec_mbus, sizeof(struct mvgbec_softc), 320 mvgbec_match, mvgbec_attach, NULL, NULL); 321 322 CFATTACH_DECL_NEW(mvgbe, sizeof(struct mvgbe_softc), 323 mvgbe_match, mvgbe_attach, NULL, NULL); 324 325 device_t mvgbec0 = NULL; 326 static int mvgbe_root_num; 327 328 struct mvgbe_port { 329 int model; 330 int unit; 331 int ports; 332 int irqs[3]; 333 int flags; 334 #define FLAGS_FIX_TQTB (1 << 0) 335 #define FLAGS_FIX_MTU (1 << 1) 336 #define FLAGS_IPG1 (1 << 2) 337 #define FLAGS_IPG2 (1 << 3) 338 #define FLAGS_HAS_PV (1 << 4) /* Has Port Version Register */ 339 } mvgbe_ports[] = { 340 { MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 }, 341 { MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 }, 342 #if 0 343 { MARVELL_DISCOVERY_LT, 0, ?, { }, 0 }, 344 { MARVELL_DISCOVERY_V, 0, ?, { }, 0 }, 345 { MARVELL_DISCOVERY_VI, 0, ?, { }, 0 }, 346 #endif 347 { MARVELL_ORION_1_88F5082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 348 { MARVELL_ORION_1_88F5180N, 0, 1, { 21 }, FLAGS_FIX_MTU }, 349 { MARVELL_ORION_1_88F5181, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 350 { MARVELL_ORION_1_88F5182, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 351 { MARVELL_ORION_2_88F5281, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 352 { MARVELL_ORION_1_88F6082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 353 { MARVELL_ORION_1_88W8660, 0, 1, { 21 }, FLAGS_FIX_MTU }, 354 355 { MARVELL_KIRKWOOD_88F6180, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 356 { MARVELL_KIRKWOOD_88F6192, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 357 { MARVELL_KIRKWOOD_88F6192, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 358 { MARVELL_KIRKWOOD_88F6281, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 359 { MARVELL_KIRKWOOD_88F6281, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 360 { MARVELL_KIRKWOOD_88F6282, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 361 { MARVELL_KIRKWOOD_88F6282, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 362 363 { MARVELL_MV78XX0_MV78100, 0, 1, { 40 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 364 { MARVELL_MV78XX0_MV78100, 1, 1, { 44 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 365 { MARVELL_MV78XX0_MV78200, 0, 1, { 40 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 366 { MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 367 { MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 368 { MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 369 370 { MARVELL_DOVE_88AP510, 0, 1, { 29 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 371 372 { MARVELL_ARMADAXP_MV78130, 0, 1, { 66 }, FLAGS_HAS_PV }, 373 { MARVELL_ARMADAXP_MV78130, 1, 1, { 70 }, FLAGS_HAS_PV }, 374 { MARVELL_ARMADAXP_MV78130, 2, 1, { 74 }, FLAGS_HAS_PV }, 375 { MARVELL_ARMADAXP_MV78160, 0, 1, { 66 }, FLAGS_HAS_PV }, 376 { MARVELL_ARMADAXP_MV78160, 1, 1, { 70 }, FLAGS_HAS_PV }, 377 { MARVELL_ARMADAXP_MV78160, 2, 1, { 74 }, FLAGS_HAS_PV }, 378 { MARVELL_ARMADAXP_MV78160, 3, 1, { 78 }, FLAGS_HAS_PV }, 379 { MARVELL_ARMADAXP_MV78230, 0, 1, { 66 }, FLAGS_HAS_PV }, 380 { MARVELL_ARMADAXP_MV78230, 1, 1, { 70 }, FLAGS_HAS_PV }, 381 { MARVELL_ARMADAXP_MV78230, 2, 1, { 74 }, FLAGS_HAS_PV }, 382 { MARVELL_ARMADAXP_MV78260, 0, 1, { 66 }, FLAGS_HAS_PV }, 383 { MARVELL_ARMADAXP_MV78260, 1, 1, { 70 }, FLAGS_HAS_PV }, 384 { MARVELL_ARMADAXP_MV78260, 2, 1, { 74 }, FLAGS_HAS_PV }, 385 { MARVELL_ARMADAXP_MV78260, 3, 1, { 78 }, FLAGS_HAS_PV }, 386 { MARVELL_ARMADAXP_MV78460, 0, 1, { 66 }, FLAGS_HAS_PV }, 387 { MARVELL_ARMADAXP_MV78460, 1, 1, { 70 }, FLAGS_HAS_PV }, 388 { MARVELL_ARMADAXP_MV78460, 2, 1, { 74 }, FLAGS_HAS_PV }, 389 { MARVELL_ARMADAXP_MV78460, 3, 1, { 78 }, FLAGS_HAS_PV }, 390 391 { MARVELL_ARMADA370_MV6707, 0, 1, { 66 }, FLAGS_HAS_PV }, 392 { MARVELL_ARMADA370_MV6707, 1, 1, { 70 }, FLAGS_HAS_PV }, 393 { MARVELL_ARMADA370_MV6710, 0, 1, { 66 }, FLAGS_HAS_PV }, 394 { MARVELL_ARMADA370_MV6710, 1, 1, { 70 }, FLAGS_HAS_PV }, 395 { MARVELL_ARMADA370_MV6W11, 0, 1, { 66 }, FLAGS_HAS_PV }, 396 { MARVELL_ARMADA370_MV6W11, 1, 1, { 70 }, FLAGS_HAS_PV }, 397 }; 398 399 400 /* ARGSUSED */ 401 static int 402 mvgbec_match(device_t parent, cfdata_t match, void *aux) 403 { 404 struct marvell_attach_args *mva = aux; 405 int i; 406 407 if (strcmp(mva->mva_name, match->cf_name) != 0) 408 return 0; 409 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 410 return 0; 411 412 for (i = 0; i < __arraycount(mvgbe_ports); i++) 413 if (mva->mva_model == mvgbe_ports[i].model) { 414 mva->mva_size = MVGBE_SIZE; 415 return 1; 416 } 417 return 0; 418 } 419 420 /* ARGSUSED */ 421 static void 422 mvgbec_attach(device_t parent, device_t self, void *aux) 423 { 424 struct mvgbec_softc *csc = device_private(self); 425 struct marvell_attach_args *mva = aux, gbea; 426 struct mvgbe_softc *port; 427 struct mii_softc *mii; 428 device_t child; 429 uint32_t phyaddr; 430 int i, j; 431 432 aprint_naive("\n"); 433 aprint_normal(": Marvell Gigabit Ethernet Controller\n"); 434 435 csc->sc_dev = self; 436 csc->sc_iot = mva->mva_iot; 437 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 438 mva->mva_size, &csc->sc_ioh)) { 439 aprint_error_dev(self, "Cannot map registers\n"); 440 return; 441 } 442 443 if (mvgbec0 == NULL) 444 mvgbec0 = self; 445 446 phyaddr = 0; 447 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr); 448 449 mutex_init(&csc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 450 451 /* Disable and clear Gigabit Ethernet Unit interrupts */ 452 MVGBE_WRITE(csc, MVGBE_EUIM, 0); 453 MVGBE_WRITE(csc, MVGBE_EUIC, 0); 454 455 mvgbec_wininit(csc, mva->mva_tags); 456 457 memset(&gbea, 0, sizeof(gbea)); 458 for (i = 0; i < __arraycount(mvgbe_ports); i++) { 459 if (mvgbe_ports[i].model != mva->mva_model || 460 mvgbe_ports[i].unit != mva->mva_unit) 461 continue; 462 463 csc->sc_flags = mvgbe_ports[i].flags; 464 465 for (j = 0; j < mvgbe_ports[i].ports; j++) { 466 gbea.mva_name = "mvgbe"; 467 gbea.mva_model = mva->mva_model; 468 gbea.mva_iot = csc->sc_iot; 469 gbea.mva_ioh = csc->sc_ioh; 470 gbea.mva_unit = j; 471 gbea.mva_dmat = mva->mva_dmat; 472 gbea.mva_irq = mvgbe_ports[i].irqs[j]; 473 child = config_found(csc->sc_dev, &gbea, mvgbec_print, 474 CFARGS(.submatch = mvgbec_search)); 475 if (child) { 476 port = device_private(child); 477 mii = LIST_FIRST(&port->sc_mii.mii_phys); 478 if (mii != NULL) 479 phyaddr |= MVGBE_PHYADDR_PHYAD(j, 480 mii->mii_phy); 481 } 482 } 483 break; 484 } 485 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr); 486 } 487 488 static int 489 mvgbec_print(void *aux, const char *pnp) 490 { 491 struct marvell_attach_args *gbea = aux; 492 493 if (pnp) 494 aprint_normal("%s at %s port %d", 495 gbea->mva_name, pnp, gbea->mva_unit); 496 else { 497 if (gbea->mva_unit != MVGBECCF_PORT_DEFAULT) 498 aprint_normal(" port %d", gbea->mva_unit); 499 if (gbea->mva_irq != MVGBECCF_IRQ_DEFAULT) 500 aprint_normal(" irq %d", gbea->mva_irq); 501 } 502 return UNCONF; 503 } 504 505 /* ARGSUSED */ 506 static int 507 mvgbec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 508 { 509 struct marvell_attach_args *gbea = aux; 510 511 if (cf->cf_loc[MVGBECCF_PORT] == gbea->mva_unit && 512 cf->cf_loc[MVGBECCF_IRQ] != MVGBECCF_IRQ_DEFAULT) 513 gbea->mva_irq = cf->cf_loc[MVGBECCF_IRQ]; 514 515 return config_match(parent, cf, aux); 516 } 517 518 static int 519 mvgbec_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 520 { 521 struct mvgbe_softc *sc = device_private(dev); 522 struct mvgbec_softc *csc; 523 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 524 uint32_t smi; 525 int i, rv = 0; 526 527 if (mvgbec0 == NULL) { 528 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 529 return -1; 530 } 531 csc = device_private(mvgbec0); 532 533 mutex_enter(&csc->sc_mtx); 534 535 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 536 DELAY(1); 537 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 538 break; 539 } 540 if (i == MVGBE_PHY_TIMEOUT) { 541 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 542 rv = ETIMEDOUT; 543 goto out; 544 } 545 546 smi = 547 MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | MVGBE_SMI_OPCODE_READ; 548 MVGBE_WRITE(csc, MVGBE_SMI, smi); 549 550 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 551 DELAY(1); 552 smi = MVGBE_READ(csc, MVGBE_SMI); 553 if (smi & MVGBE_SMI_READVALID) { 554 *val = smi & MVGBE_SMI_DATA_MASK; 555 break; 556 } 557 } 558 DPRINTFN(9, ("mvgbec_miibus_readreg: i=%d, timeout=%d\n", 559 i, MVGBE_PHY_TIMEOUT)); 560 if (i >= MVGBE_PHY_TIMEOUT) 561 rv = ETIMEDOUT; 562 563 out: 564 mutex_exit(&csc->sc_mtx); 565 566 DPRINTFN(9, ("mvgbec_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 567 phy, reg, *val)); 568 569 return rv; 570 } 571 572 static int 573 mvgbec_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 574 { 575 struct mvgbe_softc *sc = device_private(dev); 576 struct mvgbec_softc *csc; 577 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 578 uint32_t smi; 579 int i, rv = 0; 580 581 if (mvgbec0 == NULL) { 582 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 583 return -1; 584 } 585 csc = device_private(mvgbec0); 586 587 DPRINTFN(9, ("mvgbec_miibus_writereg phy=%d reg=%#x val=%#x\n", 588 phy, reg, val)); 589 590 mutex_enter(&csc->sc_mtx); 591 592 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 593 DELAY(1); 594 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 595 break; 596 } 597 if (i == MVGBE_PHY_TIMEOUT) { 598 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 599 rv = ETIMEDOUT; 600 goto out; 601 } 602 603 smi = MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | 604 MVGBE_SMI_OPCODE_WRITE | (val & MVGBE_SMI_DATA_MASK); 605 MVGBE_WRITE(csc, MVGBE_SMI, smi); 606 607 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 608 DELAY(1); 609 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 610 break; 611 } 612 613 out: 614 mutex_exit(&csc->sc_mtx); 615 616 if (i == MVGBE_PHY_TIMEOUT) { 617 aprint_error_ifnet(ifp, "phy write timed out\n"); 618 rv = ETIMEDOUT; 619 } 620 621 return rv; 622 } 623 624 static void 625 mvgbec_miibus_statchg(struct ifnet *ifp) 626 { 627 628 /* nothing to do */ 629 } 630 631 632 static void 633 mvgbec_wininit(struct mvgbec_softc *sc, enum marvell_tags *tags) 634 { 635 device_t pdev = device_parent(sc->sc_dev); 636 uint64_t base; 637 uint32_t en, ac, size; 638 int window, target, attr, rv, i; 639 640 /* First disable all address decode windows */ 641 en = MVGBE_BARE_EN_MASK; 642 MVGBE_WRITE(sc, MVGBE_BARE, en); 643 644 ac = 0; 645 for (window = 0, i = 0; 646 tags[i] != MARVELL_TAG_UNDEFINED && window < MVGBE_NWINDOW; i++) { 647 rv = marvell_winparams_by_tag(pdev, tags[i], 648 &target, &attr, &base, &size); 649 if (rv != 0 || size == 0) 650 continue; 651 652 if (base > 0xffffffffULL) { 653 if (window >= MVGBE_NREMAP) { 654 aprint_error_dev(sc->sc_dev, 655 "can't remap window %d\n", window); 656 continue; 657 } 658 MVGBE_WRITE(sc, MVGBE_HA(window), 659 (base >> 32) & 0xffffffff); 660 } 661 662 MVGBE_WRITE(sc, MVGBE_BASEADDR(window), 663 MVGBE_BASEADDR_TARGET(target) | 664 MVGBE_BASEADDR_ATTR(attr) | 665 MVGBE_BASEADDR_BASE(base)); 666 MVGBE_WRITE(sc, MVGBE_S(window), MVGBE_S_SIZE(size)); 667 668 en &= ~(1 << window); 669 /* set full access (r/w) */ 670 ac |= MVGBE_EPAP_EPAR(window, MVGBE_EPAP_AC_FA); 671 window++; 672 } 673 /* allow to access decode window */ 674 MVGBE_WRITE(sc, MVGBE_EPAP, ac); 675 676 MVGBE_WRITE(sc, MVGBE_BARE, en); 677 } 678 679 680 /* ARGSUSED */ 681 static int 682 mvgbe_match(device_t parent, cfdata_t match, void *aux) 683 { 684 struct marvell_attach_args *mva = aux; 685 uint32_t pbase, maddrh, maddrl; 686 uint8_t enaddr[ETHER_ADDR_LEN]; 687 688 if (ether_getaddr(parent, enaddr)) 689 return 1; 690 691 pbase = MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE; 692 maddrh = 693 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAH); 694 maddrl = 695 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAL); 696 if ((maddrh | maddrl) == 0) 697 return 0; 698 699 return 1; 700 } 701 702 /* ARGSUSED */ 703 static void 704 mvgbe_attach(device_t parent, device_t self, void *aux) 705 { 706 struct mvgbec_softc *csc = device_private(parent); 707 struct mvgbe_softc *sc = device_private(self); 708 struct marvell_attach_args *mva = aux; 709 struct mvgbe_txmap_entry *entry; 710 struct ifnet *ifp; 711 struct mii_data * const mii = &sc->sc_mii; 712 bus_dma_segment_t seg; 713 bus_dmamap_t dmamap; 714 int rseg, i; 715 uint32_t maddrh, maddrl; 716 uint8_t enaddr[ETHER_ADDR_LEN]; 717 void *kva; 718 719 aprint_naive("\n"); 720 aprint_normal("\n"); 721 722 sc->sc_dev = self; 723 sc->sc_port = mva->mva_unit; 724 sc->sc_iot = mva->mva_iot; 725 callout_init(&sc->sc_tick_ch, 0); 726 callout_setfunc(&sc->sc_tick_ch, mvgbe_tick, sc); 727 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 728 MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE, 729 MVGBE_PORTR_SIZE, &sc->sc_ioh)) { 730 aprint_error_dev(self, "Cannot map registers\n"); 731 return; 732 } 733 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 734 MVGBE_PORTDAFR_BASE + mva->mva_unit * MVGBE_PORTDAFR_SIZE, 735 MVGBE_PORTDAFR_SIZE, &sc->sc_dafh)) { 736 aprint_error_dev(self, 737 "Cannot map destination address filter registers\n"); 738 return; 739 } 740 sc->sc_dmat = mva->mva_dmat; 741 742 if (csc->sc_flags & FLAGS_HAS_PV) { 743 /* GbE port has Port Version register. */ 744 sc->sc_version = MVGBE_READ(sc, MVGBE_PV); 745 aprint_normal_dev(self, "Port Version 0x%x\n", sc->sc_version); 746 } 747 748 if (sc->sc_version >= 0x10) { 749 /* 750 * Armada XP 751 */ 752 753 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 754 MVGBE_PS0, sizeof(uint32_t), &sc->sc_linkup.ioh)) { 755 aprint_error_dev(self, "Cannot map linkup register\n"); 756 return; 757 } 758 sc->sc_linkup.bit = MVGBE_PS0_LINKUP; 759 csc->sc_flags |= FLAGS_IPG2; 760 } else { 761 if (bus_space_subregion(mva->mva_iot, sc->sc_ioh, 762 MVGBE_PS, sizeof(uint32_t), &sc->sc_linkup.ioh)) { 763 aprint_error_dev(self, "Cannot map linkup register\n"); 764 return; 765 } 766 sc->sc_linkup.bit = MVGBE_PS_LINKUP; 767 } 768 769 if (ether_getaddr(parent, enaddr)) { 770 maddrh = enaddr[0] << 24; 771 maddrh |= enaddr[1] << 16; 772 maddrh |= enaddr[2] << 8; 773 maddrh |= enaddr[3]; 774 maddrl = enaddr[4] << 8; 775 maddrl |= enaddr[5]; 776 MVGBE_WRITE(sc, MVGBE_MACAH, maddrh); 777 MVGBE_WRITE(sc, MVGBE_MACAL, maddrl); 778 } 779 780 maddrh = MVGBE_READ(sc, MVGBE_MACAH); 781 maddrl = MVGBE_READ(sc, MVGBE_MACAL); 782 sc->sc_enaddr[0] = maddrh >> 24; 783 sc->sc_enaddr[1] = maddrh >> 16; 784 sc->sc_enaddr[2] = maddrh >> 8; 785 sc->sc_enaddr[3] = maddrh >> 0; 786 sc->sc_enaddr[4] = maddrl >> 8; 787 sc->sc_enaddr[5] = maddrl >> 0; 788 aprint_normal_dev(self, "Ethernet address %s\n", 789 ether_sprintf(sc->sc_enaddr)); 790 791 /* clear all ethernet port interrupts */ 792 MVGBE_WRITE(sc, MVGBE_IC, 0); 793 MVGBE_WRITE(sc, MVGBE_ICE, 0); 794 795 marvell_intr_establish(mva->mva_irq, IPL_NET, mvgbe_intr, sc); 796 797 /* Allocate the descriptor queues. */ 798 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 799 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 800 aprint_error_dev(self, "can't alloc rx buffers\n"); 801 return; 802 } 803 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, 804 sizeof(struct mvgbe_ring_data), &kva, BUS_DMA_NOWAIT)) { 805 aprint_error_dev(self, "can't map dma buffers (%lu bytes)\n", 806 (u_long)sizeof(struct mvgbe_ring_data)); 807 goto fail1; 808 } 809 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 1, 810 sizeof(struct mvgbe_ring_data), 0, BUS_DMA_NOWAIT, 811 &sc->sc_ring_map)) { 812 aprint_error_dev(self, "can't create dma map\n"); 813 goto fail2; 814 } 815 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ring_map, kva, 816 sizeof(struct mvgbe_ring_data), NULL, BUS_DMA_NOWAIT)) { 817 aprint_error_dev(self, "can't load dma map\n"); 818 goto fail3; 819 } 820 for (i = 0; i < MVGBE_RX_RING_CNT; i++) 821 sc->sc_cdata.mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 822 823 SIMPLEQ_INIT(&sc->sc_txmap_head); 824 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 825 sc->sc_cdata.mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 826 827 if (bus_dmamap_create(sc->sc_dmat, 828 MVGBE_JLEN, MVGBE_NTXSEG, MVGBE_JLEN, 0, 829 BUS_DMA_NOWAIT, &dmamap)) { 830 aprint_error_dev(self, "Can't create TX dmamap\n"); 831 goto fail4; 832 } 833 834 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 835 entry->dmamap = dmamap; 836 SIMPLEQ_INSERT_HEAD(&sc->sc_txmap_head, entry, link); 837 } 838 839 sc->sc_rdata = (struct mvgbe_ring_data *)kva; 840 memset(sc->sc_rdata, 0, sizeof(struct mvgbe_ring_data)); 841 842 /* 843 * We can support 802.1Q VLAN-sized frames and jumbo 844 * Ethernet frames. 845 */ 846 sc->sc_ethercom.ec_capabilities |= 847 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 848 849 /* Try to allocate memory for jumbo buffers. */ 850 if (mvgbe_alloc_jumbo_mem(sc)) { 851 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 852 goto fail4; 853 } 854 855 ifp = &sc->sc_ethercom.ec_if; 856 ifp->if_softc = sc; 857 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 858 ifp->if_start = mvgbe_start; 859 ifp->if_ioctl = mvgbe_ioctl; 860 ifp->if_init = mvgbe_init; 861 ifp->if_stop = mvgbe_stop; 862 ifp->if_watchdog = mvgbe_watchdog; 863 /* 864 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 865 */ 866 sc->sc_ethercom.ec_if.if_capabilities |= 867 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 868 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 869 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 870 /* 871 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums. 872 */ 873 sc->sc_ethercom.ec_if.if_capabilities &= ~IFCAP_CSUM_TCPv4_Tx; 874 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(MVGBE_TX_RING_CNT - 1, IFQ_MAXLEN)); 875 IFQ_SET_READY(&ifp->if_snd); 876 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 877 878 mvgbe_stop(ifp, 0); 879 880 /* 881 * Do MII setup. 882 */ 883 mii->mii_ifp = ifp; 884 mii->mii_readreg = mvgbec_miibus_readreg; 885 mii->mii_writereg = mvgbec_miibus_writereg; 886 mii->mii_statchg = mvgbec_miibus_statchg; 887 888 sc->sc_ethercom.ec_mii = mii; 889 ifmedia_init(&mii->mii_media, 0, mvgbe_mediachange, mvgbe_mediastatus); 890 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 891 parent == mvgbec0 ? 0 : 1, 0); 892 if (LIST_FIRST(&mii->mii_phys) == NULL) { 893 aprint_error_dev(self, "no PHY found!\n"); 894 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 895 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 896 } else 897 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 898 899 /* 900 * Call MI attach routines. 901 */ 902 if_attach(ifp); 903 if_deferred_start_init(ifp, NULL); 904 905 ether_ifattach(ifp, sc->sc_enaddr); 906 ether_set_ifflags_cb(&sc->sc_ethercom, mvgbe_ifflags_cb); 907 908 sysctl_mvgbe_init(sc); 909 #ifdef MVGBE_EVENT_COUNTERS 910 /* Attach event counters. */ 911 evcnt_attach_dynamic(&sc->sc_ev_rxoverrun, EVCNT_TYPE_MISC, 912 NULL, device_xname(sc->sc_dev), "rxoverrun"); 913 evcnt_attach_dynamic(&sc->sc_ev_wdogsoft, EVCNT_TYPE_MISC, 914 NULL, device_xname(sc->sc_dev), "wdogsoft"); 915 #endif 916 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 917 RND_TYPE_NET, RND_FLAG_DEFAULT); 918 919 return; 920 921 fail4: 922 while ((entry = SIMPLEQ_FIRST(&sc->sc_txmap_head)) != NULL) { 923 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 924 bus_dmamap_destroy(sc->sc_dmat, entry->dmamap); 925 } 926 bus_dmamap_unload(sc->sc_dmat, sc->sc_ring_map); 927 fail3: 928 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ring_map); 929 fail2: 930 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct mvgbe_ring_data)); 931 fail1: 932 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 933 return; 934 } 935 936 static int 937 mvgbe_ipginttx(struct mvgbec_softc *csc, struct mvgbe_softc *sc, 938 unsigned int ipginttx) 939 { 940 uint32_t reg; 941 reg = MVGBE_READ(sc, MVGBE_PTFUT); 942 943 if (csc->sc_flags & FLAGS_IPG2) { 944 if (ipginttx > MVGBE_PTFUT_IPGINTTX_V2_MAX) 945 return -1; 946 reg &= ~MVGBE_PTFUT_IPGINTTX_V2_MASK; 947 reg |= MVGBE_PTFUT_IPGINTTX_V2(ipginttx); 948 } else if (csc->sc_flags & FLAGS_IPG1) { 949 if (ipginttx > MVGBE_PTFUT_IPGINTTX_V1_MAX) 950 return -1; 951 reg &= ~MVGBE_PTFUT_IPGINTTX_V1_MASK; 952 reg |= MVGBE_PTFUT_IPGINTTX_V1(ipginttx); 953 } 954 MVGBE_WRITE(sc, MVGBE_PTFUT, reg); 955 956 return 0; 957 } 958 959 static int 960 mvgbe_ipgintrx(struct mvgbec_softc *csc, struct mvgbe_softc *sc, 961 unsigned int ipgintrx) 962 { 963 uint32_t reg; 964 reg = MVGBE_READ(sc, MVGBE_SDC); 965 966 if (csc->sc_flags & FLAGS_IPG2) { 967 if (ipgintrx > MVGBE_SDC_IPGINTRX_V2_MAX) 968 return -1; 969 reg &= ~MVGBE_SDC_IPGINTRX_V2_MASK; 970 reg |= MVGBE_SDC_IPGINTRX_V2(ipgintrx); 971 } else if (csc->sc_flags & FLAGS_IPG1) { 972 if (ipgintrx > MVGBE_SDC_IPGINTRX_V1_MAX) 973 return -1; 974 reg &= ~MVGBE_SDC_IPGINTRX_V1_MASK; 975 reg |= MVGBE_SDC_IPGINTRX_V1(ipgintrx); 976 } 977 MVGBE_WRITE(sc, MVGBE_SDC, reg); 978 979 return 0; 980 } 981 982 static void 983 mvgbe_tick(void *arg) 984 { 985 struct mvgbe_softc *sc = arg; 986 struct mii_data *mii = &sc->sc_mii; 987 int s; 988 989 s = splnet(); 990 mii_tick(mii); 991 /* Need more work */ 992 MVGBE_EVCNT_ADD(&sc->sc_ev_rxoverrun, MVGBE_READ(sc, MVGBE_POFC)); 993 splx(s); 994 995 callout_schedule(&sc->sc_tick_ch, hz); 996 } 997 998 static int 999 mvgbe_intr(void *arg) 1000 { 1001 struct mvgbe_softc *sc = arg; 1002 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1003 uint32_t ic, ice, datum = 0; 1004 int claimed = 0; 1005 1006 for (;;) { 1007 ice = MVGBE_READ(sc, MVGBE_ICE); 1008 ic = MVGBE_READ(sc, MVGBE_IC); 1009 1010 DPRINTFN(3, ("mvgbe_intr: ic=%#x, ice=%#x\n", ic, ice)); 1011 if (ic == 0 && ice == 0) 1012 break; 1013 1014 datum = datum ^ ic ^ ice; 1015 1016 MVGBE_WRITE(sc, MVGBE_IC, ~ic); 1017 MVGBE_WRITE(sc, MVGBE_ICE, ~ice); 1018 1019 claimed = 1; 1020 1021 if (!(ifp->if_flags & IFF_RUNNING)) 1022 break; 1023 1024 if (ice & MVGBE_ICE_LINKCHG) { 1025 if (MVGBE_IS_LINKUP(sc)) { 1026 /* Enable port RX and TX. */ 1027 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1028 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1029 } else { 1030 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ(0)); 1031 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0)); 1032 } 1033 1034 /* Notify link change event to mii layer */ 1035 mii_pollstat(&sc->sc_mii); 1036 } 1037 1038 if (ic & (MVGBE_IC_RXBUF | MVGBE_IC_RXERROR)) 1039 mvgbe_rxeof(sc); 1040 1041 if (ice & (MVGBE_ICE_TXBUF_MASK | MVGBE_ICE_TXERR_MASK)) 1042 mvgbe_txeof(sc); 1043 } 1044 1045 if_schedule_deferred_start(ifp); 1046 1047 rnd_add_uint32(&sc->sc_rnd_source, datum); 1048 1049 return claimed; 1050 } 1051 1052 static void 1053 mvgbe_start(struct ifnet *ifp) 1054 { 1055 struct mvgbe_softc *sc = ifp->if_softc; 1056 struct mbuf *m_head = NULL; 1057 uint32_t idx = sc->sc_cdata.mvgbe_tx_prod; 1058 int pkts = 0; 1059 1060 DPRINTFN(3, ("mvgbe_start (idx %d, tx_chain[idx] %p)\n", idx, 1061 sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf)); 1062 1063 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1064 return; 1065 /* If Link is DOWN, can't start TX */ 1066 if (!MVGBE_IS_LINKUP(sc)) 1067 return; 1068 1069 while (sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf == NULL) { 1070 IFQ_POLL(&ifp->if_snd, m_head); 1071 if (m_head == NULL) 1072 break; 1073 1074 /* 1075 * Pack the data into the transmit ring. If we 1076 * don't have room, set the OACTIVE flag and wait 1077 * for the NIC to drain the ring. 1078 */ 1079 if (mvgbe_encap(sc, m_head, &idx)) { 1080 if (sc->sc_cdata.mvgbe_tx_cnt > 0) 1081 ifp->if_flags |= IFF_OACTIVE; 1082 break; 1083 } 1084 1085 /* now we are committed to transmit the packet */ 1086 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1087 pkts++; 1088 1089 /* 1090 * If there's a BPF listener, bounce a copy of this frame 1091 * to him. 1092 */ 1093 bpf_mtap(ifp, m_head, BPF_D_OUT); 1094 } 1095 if (pkts == 0) 1096 return; 1097 1098 /* Transmit at Queue 0 */ 1099 if (idx != sc->sc_cdata.mvgbe_tx_prod) { 1100 sc->sc_cdata.mvgbe_tx_prod = idx; 1101 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1102 1103 /* 1104 * Set a timeout in case the chip goes out to lunch. 1105 */ 1106 ifp->if_timer = 1; 1107 sc->sc_wdogsoft = 1; 1108 } 1109 } 1110 1111 static int 1112 mvgbe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1113 { 1114 struct mvgbe_softc *sc = ifp->if_softc; 1115 int s, error = 0; 1116 1117 s = splnet(); 1118 1119 switch (cmd) { 1120 default: 1121 DPRINTFN(2, ("mvgbe_ioctl ETHER\n")); 1122 error = ether_ioctl(ifp, cmd, data); 1123 if (error == ENETRESET) { 1124 if (ifp->if_flags & IFF_RUNNING) { 1125 mvgbe_filter_setup(sc); 1126 } 1127 error = 0; 1128 } 1129 break; 1130 } 1131 1132 splx(s); 1133 1134 return error; 1135 } 1136 1137 static int 1138 mvgbe_init(struct ifnet *ifp) 1139 { 1140 struct mvgbe_softc *sc = ifp->if_softc; 1141 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 1142 struct mii_data *mii = &sc->sc_mii; 1143 uint32_t reg; 1144 int i; 1145 1146 DPRINTFN(2, ("mvgbe_init\n")); 1147 1148 /* Cancel pending I/O and free all RX/TX buffers. */ 1149 mvgbe_stop(ifp, 0); 1150 1151 /* clear all ethernet port interrupts */ 1152 MVGBE_WRITE(sc, MVGBE_IC, 0); 1153 MVGBE_WRITE(sc, MVGBE_ICE, 0); 1154 1155 /* Init TX/RX descriptors */ 1156 if (mvgbe_init_tx_ring(sc) == ENOBUFS) { 1157 aprint_error_ifnet(ifp, 1158 "initialization failed: no memory for tx buffers\n"); 1159 return ENOBUFS; 1160 } 1161 if (mvgbe_init_rx_ring(sc) == ENOBUFS) { 1162 aprint_error_ifnet(ifp, 1163 "initialization failed: no memory for rx buffers\n"); 1164 return ENOBUFS; 1165 } 1166 1167 if ((csc->sc_flags & FLAGS_IPG1) || (csc->sc_flags & FLAGS_IPG2)) { 1168 sc->sc_ipginttx = MVGBE_IPGINTTX_DEFAULT; 1169 sc->sc_ipgintrx = MVGBE_IPGINTRX_DEFAULT; 1170 } 1171 if (csc->sc_flags & FLAGS_FIX_MTU) 1172 MVGBE_WRITE(sc, MVGBE_MTU, 0); /* hw reset value is wrong */ 1173 if (sc->sc_version >= 0x10) { 1174 MVGBE_WRITE(csc, MVGBE_PANC, 1175 MVGBE_PANC_FORCELINKPASS | 1176 MVGBE_PANC_INBANDANBYPASSEN | 1177 MVGBE_PANC_SETMIISPEED | 1178 MVGBE_PANC_SETGMIISPEED | 1179 MVGBE_PANC_ANSPEEDEN | 1180 MVGBE_PANC_SETFCEN | 1181 MVGBE_PANC_PAUSEADV | 1182 MVGBE_PANC_SETFULLDX | 1183 MVGBE_PANC_ANDUPLEXEN | 1184 MVGBE_PANC_RESERVED); 1185 MVGBE_WRITE(csc, MVGBE_PMACC0, 1186 MVGBE_PMACC0_RESERVED | 1187 MVGBE_PMACC0_FRAMESIZELIMIT(1600)); 1188 reg = MVGBE_READ(csc, MVGBE_PMACC2); 1189 reg &= MVGBE_PMACC2_PCSEN; /* keep PCSEN bit */ 1190 MVGBE_WRITE(csc, MVGBE_PMACC2, 1191 reg | MVGBE_PMACC2_RESERVED | MVGBE_PMACC2_RGMIIEN); 1192 1193 MVGBE_WRITE(sc, MVGBE_PXCX, 1194 MVGBE_READ(sc, MVGBE_PXCX) & ~MVGBE_PXCX_TXCRCDIS); 1195 1196 #ifndef MULTIPROCESSOR 1197 MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_BM); 1198 #else 1199 MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_EDM); 1200 #endif 1201 } else { 1202 MVGBE_WRITE(sc, MVGBE_PSC, 1203 MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */ 1204 MVGBE_PSC_RESERVED | /* Must be set to 1 */ 1205 MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */ 1206 MVGBE_PSC_MRU(MVGBE_PSC_MRU_9022) | /* we want 9k */ 1207 MVGBE_PSC_SETFULLDX); /* Set_FullDx */ 1208 /* XXXX: mvgbe(4) always use RGMII. */ 1209 MVGBE_WRITE(sc, MVGBE_PSC1, 1210 MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN); 1211 /* XXXX: Also always Weighted Round-Robin Priority Mode */ 1212 MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0)); 1213 1214 sc->sc_cmdsts_opts = MVGBE_TX_GENERATE_CRC; 1215 } 1216 1217 MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0)); 1218 MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0)); 1219 1220 if (csc->sc_flags & FLAGS_FIX_TQTB) { 1221 /* 1222 * Queue 0 (offset 0x72700) must be programmed to 0x3fffffff. 1223 * And offset 0x72704 must be programmed to 0x03ffffff. 1224 * Queue 1 through 7 must be programmed to 0x0. 1225 */ 1226 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(0), 0x3fffffff); 1227 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(0), 0x03ffffff); 1228 for (i = 1; i < 8; i++) { 1229 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0); 1230 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0); 1231 } 1232 } else if (sc->sc_version < 0x10) 1233 for (i = 1; i < 8; i++) { 1234 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff); 1235 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff); 1236 MVGBE_WRITE(sc, MVGBE_TQAC(i), 0xfc0000ff); 1237 } 1238 1239 MVGBE_WRITE(sc, MVGBE_PXC, MVGBE_PXC_RXCS); 1240 MVGBE_WRITE(sc, MVGBE_PXCX, 0); 1241 1242 /* Set SDC register except IPGINT bits */ 1243 MVGBE_WRITE(sc, MVGBE_SDC, 1244 MVGBE_SDC_RXBSZ_16_64BITWORDS | 1245 #ifndef MVGBE_BIG_ENDIAN 1246 MVGBE_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */ 1247 MVGBE_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */ 1248 #endif 1249 MVGBE_SDC_TXBSZ_16_64BITWORDS); 1250 /* And then set IPGINT bits */ 1251 mvgbe_ipgintrx(csc, sc, sc->sc_ipgintrx); 1252 1253 /* Tx side */ 1254 MVGBE_WRITE(sc, MVGBE_PTFUT, 0); 1255 mvgbe_ipginttx(csc, sc, sc->sc_ipginttx); 1256 1257 mvgbe_filter_setup(sc); 1258 1259 mii_mediachg(mii); 1260 1261 /* Enable port */ 1262 if (sc->sc_version >= 0x10) { 1263 reg = MVGBE_READ(csc, MVGBE_PMACC0); 1264 MVGBE_WRITE(csc, MVGBE_PMACC0, reg | MVGBE_PMACC0_PORTEN); 1265 } else { 1266 reg = MVGBE_READ(sc, MVGBE_PSC); 1267 MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN); 1268 } 1269 1270 /* If Link is UP, Start RX and TX traffic */ 1271 if (MVGBE_IS_LINKUP(sc)) { 1272 /* Enable port RX/TX. */ 1273 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1274 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1275 } 1276 1277 /* Enable interrupt masks */ 1278 MVGBE_WRITE(sc, MVGBE_PIM, 1279 MVGBE_IC_RXBUF | 1280 MVGBE_IC_EXTEND | 1281 MVGBE_IC_RXBUFQ_MASK | 1282 MVGBE_IC_RXERROR | 1283 MVGBE_IC_RXERRQ_MASK); 1284 MVGBE_WRITE(sc, MVGBE_PEIM, 1285 MVGBE_ICE_TXBUF_MASK | 1286 MVGBE_ICE_TXERR_MASK | 1287 MVGBE_ICE_LINKCHG); 1288 1289 callout_schedule(&sc->sc_tick_ch, hz); 1290 1291 ifp->if_flags |= IFF_RUNNING; 1292 ifp->if_flags &= ~IFF_OACTIVE; 1293 1294 return 0; 1295 } 1296 1297 /* ARGSUSED */ 1298 static void 1299 mvgbe_stop(struct ifnet *ifp, int disable) 1300 { 1301 struct mvgbe_softc *sc = ifp->if_softc; 1302 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 1303 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1304 uint32_t reg, txinprog, txfifoemp; 1305 int i, cnt; 1306 1307 DPRINTFN(2, ("mvgbe_stop\n")); 1308 1309 callout_stop(&sc->sc_tick_ch); 1310 1311 /* Stop Rx port activity. Check port Rx activity. */ 1312 reg = MVGBE_READ(sc, MVGBE_RQC); 1313 if (reg & MVGBE_RQC_ENQ_MASK) 1314 /* Issue stop command for active channels only */ 1315 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg)); 1316 1317 /* Stop Tx port activity. Check port Tx activity. */ 1318 if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ(0)) 1319 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0)); 1320 1321 /* Force link down */ 1322 if (sc->sc_version >= 0x10) { 1323 reg = MVGBE_READ(csc, MVGBE_PANC); 1324 MVGBE_WRITE(csc, MVGBE_PANC, reg | MVGBE_PANC_FORCELINKFAIL); 1325 1326 txinprog = MVGBE_PS_TXINPROG_(0); 1327 txfifoemp = MVGBE_PS_TXFIFOEMP_(0); 1328 } else { 1329 reg = MVGBE_READ(sc, MVGBE_PSC); 1330 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL); 1331 1332 txinprog = MVGBE_PS_TXINPROG; 1333 txfifoemp = MVGBE_PS_TXFIFOEMP; 1334 } 1335 1336 #define RX_DISABLE_TIMEOUT 0x1000000 1337 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 1338 /* Wait for all Rx activity to terminate. */ 1339 cnt = 0; 1340 do { 1341 if (cnt >= RX_DISABLE_TIMEOUT) { 1342 aprint_error_ifnet(ifp, 1343 "timeout for RX stopped. rqc 0x%x\n", reg); 1344 break; 1345 } 1346 cnt++; 1347 1348 /* 1349 * Check Receive Queue Command register that all Rx queues 1350 * are stopped 1351 */ 1352 reg = MVGBE_READ(sc, MVGBE_RQC); 1353 } while (reg & 0xff); 1354 1355 /* Double check to verify that TX FIFO is empty */ 1356 cnt = 0; 1357 while (1) { 1358 do { 1359 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1360 aprint_error_ifnet(ifp, 1361 "timeout for TX FIFO empty. status 0x%x\n", 1362 reg); 1363 break; 1364 } 1365 cnt++; 1366 1367 reg = MVGBE_READ(sc, MVGBE_PS); 1368 } while (!(reg & txfifoemp) || reg & txinprog); 1369 1370 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) 1371 break; 1372 1373 /* Double check */ 1374 reg = MVGBE_READ(sc, MVGBE_PS); 1375 if (reg & txfifoemp && !(reg & txinprog)) 1376 break; 1377 else 1378 aprint_error_ifnet(ifp, 1379 "TX FIFO empty double check failed." 1380 " %d loops, status 0x%x\n", cnt, reg); 1381 } 1382 1383 /* Reset the Enable bit */ 1384 if (sc->sc_version >= 0x10) { 1385 reg = MVGBE_READ(csc, MVGBE_PMACC0); 1386 MVGBE_WRITE(csc, MVGBE_PMACC0, reg & ~MVGBE_PMACC0_PORTEN); 1387 } else { 1388 reg = MVGBE_READ(sc, MVGBE_PSC); 1389 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN); 1390 } 1391 1392 /* 1393 * Disable and clear interrupts 1394 * 0) controller interrupt 1395 * 1) port interrupt cause 1396 * 2) port interrupt mask 1397 */ 1398 MVGBE_WRITE(csc, MVGBE_EUIM, 0); 1399 MVGBE_WRITE(csc, MVGBE_EUIC, 0); 1400 MVGBE_WRITE(sc, MVGBE_IC, 0); 1401 MVGBE_WRITE(sc, MVGBE_ICE, 0); 1402 MVGBE_WRITE(sc, MVGBE_PIM, 0); 1403 MVGBE_WRITE(sc, MVGBE_PEIM, 0); 1404 1405 /* Free RX and TX mbufs still in the queues. */ 1406 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1407 m_freem(cdata->mvgbe_rx_chain[i].mvgbe_mbuf); 1408 cdata->mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 1409 } 1410 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1411 m_freem(cdata->mvgbe_tx_chain[i].mvgbe_mbuf); 1412 cdata->mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 1413 } 1414 1415 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1416 } 1417 1418 static void 1419 mvgbe_watchdog(struct ifnet *ifp) 1420 { 1421 struct mvgbe_softc *sc = ifp->if_softc; 1422 1423 /* 1424 * Reclaim first as there is a possibility of losing Tx completion 1425 * interrupts. 1426 */ 1427 mvgbe_txeof(sc); 1428 if (sc->sc_cdata.mvgbe_tx_cnt != 0) { 1429 if (sc->sc_wdogsoft) { 1430 /* 1431 * There is race condition between CPU and DMA 1432 * engine. When DMA engine encounters queue end, 1433 * it clears MVGBE_TQC_ENQ bit. 1434 */ 1435 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1436 ifp->if_timer = 5; 1437 sc->sc_wdogsoft = 0; 1438 MVGBE_EVCNT_INCR(&sc->sc_ev_wdogsoft); 1439 } else { 1440 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1441 1442 if_statinc(ifp, if_oerrors); 1443 1444 mvgbe_init(ifp); 1445 } 1446 } 1447 } 1448 1449 static int 1450 mvgbe_ifflags_cb(struct ethercom *ec) 1451 { 1452 struct ifnet *ifp = &ec->ec_if; 1453 struct mvgbe_softc *sc = ifp->if_softc; 1454 u_short change = ifp->if_flags ^ sc->sc_if_flags; 1455 1456 if (change != 0) 1457 sc->sc_if_flags = ifp->if_flags; 1458 1459 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 1460 return ENETRESET; 1461 1462 if ((change & IFF_PROMISC) != 0) 1463 mvgbe_filter_setup(sc); 1464 1465 return 0; 1466 } 1467 1468 /* 1469 * Set media options. 1470 */ 1471 static int 1472 mvgbe_mediachange(struct ifnet *ifp) 1473 { 1474 return ether_mediachange(ifp); 1475 } 1476 1477 /* 1478 * Report current media status. 1479 */ 1480 static void 1481 mvgbe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1482 { 1483 ether_mediastatus(ifp, ifmr); 1484 } 1485 1486 1487 static int 1488 mvgbe_init_rx_ring(struct mvgbe_softc *sc) 1489 { 1490 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1491 struct mvgbe_ring_data *rd = sc->sc_rdata; 1492 int i; 1493 1494 memset(rd->mvgbe_rx_ring, 0, 1495 sizeof(struct mvgbe_rx_desc) * MVGBE_RX_RING_CNT); 1496 1497 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1498 cd->mvgbe_rx_chain[i].mvgbe_desc = 1499 &rd->mvgbe_rx_ring[i]; 1500 if (i == MVGBE_RX_RING_CNT - 1) { 1501 cd->mvgbe_rx_chain[i].mvgbe_next = 1502 &cd->mvgbe_rx_chain[0]; 1503 rd->mvgbe_rx_ring[i].nextdescptr = 1504 H2MVGBE32(MVGBE_RX_RING_ADDR(sc, 0)); 1505 } else { 1506 cd->mvgbe_rx_chain[i].mvgbe_next = 1507 &cd->mvgbe_rx_chain[i + 1]; 1508 rd->mvgbe_rx_ring[i].nextdescptr = 1509 H2MVGBE32(MVGBE_RX_RING_ADDR(sc, i + 1)); 1510 } 1511 } 1512 1513 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1514 if (mvgbe_newbuf(sc, i, NULL, 1515 sc->sc_cdata.mvgbe_rx_jumbo_map) == ENOBUFS) { 1516 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1517 "failed alloc of %dth mbuf\n", i); 1518 return ENOBUFS; 1519 } 1520 } 1521 sc->sc_cdata.mvgbe_rx_prod = 0; 1522 sc->sc_cdata.mvgbe_rx_cons = 0; 1523 1524 return 0; 1525 } 1526 1527 static int 1528 mvgbe_init_tx_ring(struct mvgbe_softc *sc) 1529 { 1530 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1531 struct mvgbe_ring_data *rd = sc->sc_rdata; 1532 int i; 1533 1534 memset(sc->sc_rdata->mvgbe_tx_ring, 0, 1535 sizeof(struct mvgbe_tx_desc) * MVGBE_TX_RING_CNT); 1536 1537 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1538 cd->mvgbe_tx_chain[i].mvgbe_desc = 1539 &rd->mvgbe_tx_ring[i]; 1540 if (i == MVGBE_TX_RING_CNT - 1) { 1541 cd->mvgbe_tx_chain[i].mvgbe_next = 1542 &cd->mvgbe_tx_chain[0]; 1543 rd->mvgbe_tx_ring[i].nextdescptr = 1544 H2MVGBE32(MVGBE_TX_RING_ADDR(sc, 0)); 1545 } else { 1546 cd->mvgbe_tx_chain[i].mvgbe_next = 1547 &cd->mvgbe_tx_chain[i + 1]; 1548 rd->mvgbe_tx_ring[i].nextdescptr = 1549 H2MVGBE32(MVGBE_TX_RING_ADDR(sc, i + 1)); 1550 } 1551 rd->mvgbe_tx_ring[i].cmdsts = 1552 H2MVGBE32(MVGBE_BUFFER_OWNED_BY_HOST); 1553 } 1554 1555 sc->sc_cdata.mvgbe_tx_prod = 0; 1556 sc->sc_cdata.mvgbe_tx_cons = 0; 1557 sc->sc_cdata.mvgbe_tx_cnt = 0; 1558 1559 MVGBE_CDTXSYNC(sc, 0, MVGBE_TX_RING_CNT, 1560 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1561 1562 return 0; 1563 } 1564 1565 static int 1566 mvgbe_newbuf(struct mvgbe_softc *sc, int i, struct mbuf *m, 1567 bus_dmamap_t dmamap) 1568 { 1569 struct mbuf *m_new = NULL; 1570 struct mvgbe_chain *c; 1571 struct mvgbe_rx_desc *r; 1572 int align; 1573 vaddr_t offset; 1574 uint16_t bufsize; 1575 1576 if (m == NULL) { 1577 void *buf = NULL; 1578 1579 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1580 if (m_new == NULL) { 1581 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1582 "no memory for rx list -- packet dropped!\n"); 1583 return ENOBUFS; 1584 } 1585 1586 /* Allocate the jumbo buffer */ 1587 buf = mvgbe_jalloc(sc); 1588 if (buf == NULL) { 1589 m_freem(m_new); 1590 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 1591 "dropped!\n", sc->sc_ethercom.ec_if.if_xname)); 1592 return ENOBUFS; 1593 } 1594 1595 /* Attach the buffer to the mbuf */ 1596 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1597 MEXTADD(m_new, buf, MVGBE_JLEN, 0, mvgbe_jfree, sc); 1598 } else { 1599 /* 1600 * We're re-using a previously allocated mbuf; 1601 * be sure to re-init pointers and lengths to 1602 * default values. 1603 */ 1604 m_new = m; 1605 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1606 m_new->m_data = m_new->m_ext.ext_buf; 1607 } 1608 align = (u_long)m_new->m_data & MVGBE_RXBUF_MASK; 1609 if (align != 0) { 1610 DPRINTFN(1,("align = %d\n", align)); 1611 m_adj(m_new, MVGBE_RXBUF_ALIGN - align); 1612 } 1613 1614 c = &sc->sc_cdata.mvgbe_rx_chain[i]; 1615 r = c->mvgbe_desc; 1616 c->mvgbe_mbuf = m_new; 1617 offset = (vaddr_t)m_new->m_data - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf; 1618 r->bufptr = H2MVGBE32(dmamap->dm_segs[0].ds_addr + offset); 1619 bufsize = MVGBE_JLEN & ~MVGBE_RXBUF_MASK; 1620 r->bufsize = H2MVGBE16(bufsize); 1621 r->cmdsts = 1622 H2MVGBE32(MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT); 1623 1624 /* Invalidate RX buffer */ 1625 bus_dmamap_sync(sc->sc_dmat, dmamap, offset, bufsize, 1626 BUS_DMASYNC_PREREAD); 1627 1628 MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1629 1630 return 0; 1631 } 1632 1633 /* 1634 * Memory management for jumbo frames. 1635 */ 1636 1637 static int 1638 mvgbe_alloc_jumbo_mem(struct mvgbe_softc *sc) 1639 { 1640 char *ptr, *kva; 1641 bus_dma_segment_t seg; 1642 int i, rseg, state, error; 1643 struct mvgbe_jpool_entry *entry; 1644 1645 state = error = 0; 1646 1647 /* Grab a big chunk o' storage. */ 1648 if (bus_dmamem_alloc(sc->sc_dmat, MVGBE_JMEM, PAGE_SIZE, 0, 1649 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1650 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 1651 return ENOBUFS; 1652 } 1653 1654 state = 1; 1655 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, MVGBE_JMEM, 1656 (void **)&kva, BUS_DMA_NOWAIT)) { 1657 aprint_error_dev(sc->sc_dev, 1658 "can't map dma buffers (%d bytes)\n", MVGBE_JMEM); 1659 error = ENOBUFS; 1660 goto out; 1661 } 1662 1663 state = 2; 1664 if (bus_dmamap_create(sc->sc_dmat, MVGBE_JMEM, 1, MVGBE_JMEM, 0, 1665 BUS_DMA_NOWAIT, &sc->sc_cdata.mvgbe_rx_jumbo_map)) { 1666 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 1667 error = ENOBUFS; 1668 goto out; 1669 } 1670 1671 state = 3; 1672 if (bus_dmamap_load(sc->sc_dmat, sc->sc_cdata.mvgbe_rx_jumbo_map, 1673 kva, MVGBE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1674 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 1675 error = ENOBUFS; 1676 goto out; 1677 } 1678 1679 state = 4; 1680 sc->sc_cdata.mvgbe_jumbo_buf = (void *)kva; 1681 DPRINTFN(1,("mvgbe_jumbo_buf = %p\n", sc->sc_cdata.mvgbe_jumbo_buf)); 1682 1683 LIST_INIT(&sc->sc_jfree_listhead); 1684 LIST_INIT(&sc->sc_jinuse_listhead); 1685 1686 /* 1687 * Now divide it up into 9K pieces and save the addresses 1688 * in an array. 1689 */ 1690 ptr = sc->sc_cdata.mvgbe_jumbo_buf; 1691 for (i = 0; i < MVGBE_JSLOTS; i++) { 1692 sc->sc_cdata.mvgbe_jslots[i] = ptr; 1693 ptr += MVGBE_JLEN; 1694 entry = kmem_alloc(sizeof(struct mvgbe_jpool_entry), KM_SLEEP); 1695 entry->slot = i; 1696 if (i) 1697 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, 1698 jpool_entries); 1699 else 1700 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, 1701 jpool_entries); 1702 } 1703 out: 1704 if (error != 0) { 1705 switch (state) { 1706 case 4: 1707 bus_dmamap_unload(sc->sc_dmat, 1708 sc->sc_cdata.mvgbe_rx_jumbo_map); 1709 case 3: 1710 bus_dmamap_destroy(sc->sc_dmat, 1711 sc->sc_cdata.mvgbe_rx_jumbo_map); 1712 case 2: 1713 bus_dmamem_unmap(sc->sc_dmat, kva, MVGBE_JMEM); 1714 case 1: 1715 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1716 break; 1717 default: 1718 break; 1719 } 1720 } 1721 1722 return error; 1723 } 1724 1725 /* 1726 * Allocate a jumbo buffer. 1727 */ 1728 static void * 1729 mvgbe_jalloc(struct mvgbe_softc *sc) 1730 { 1731 struct mvgbe_jpool_entry *entry; 1732 1733 entry = LIST_FIRST(&sc->sc_jfree_listhead); 1734 1735 if (entry == NULL) 1736 return NULL; 1737 1738 LIST_REMOVE(entry, jpool_entries); 1739 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, jpool_entries); 1740 return sc->sc_cdata.mvgbe_jslots[entry->slot]; 1741 } 1742 1743 /* 1744 * Release a jumbo buffer. 1745 */ 1746 static void 1747 mvgbe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1748 { 1749 struct mvgbe_jpool_entry *entry; 1750 struct mvgbe_softc *sc; 1751 int i, s; 1752 1753 /* Extract the softc struct pointer. */ 1754 sc = (struct mvgbe_softc *)arg; 1755 1756 if (sc == NULL) 1757 panic("%s: can't find softc pointer!", __func__); 1758 1759 /* calculate the slot this buffer belongs to */ 1760 1761 i = ((vaddr_t)buf - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf) / MVGBE_JLEN; 1762 1763 if ((i < 0) || (i >= MVGBE_JSLOTS)) 1764 panic("%s: asked to free buffer that we don't manage!", 1765 __func__); 1766 1767 s = splvm(); 1768 entry = LIST_FIRST(&sc->sc_jinuse_listhead); 1769 if (entry == NULL) 1770 panic("%s: buffer not in use!", __func__); 1771 entry->slot = i; 1772 LIST_REMOVE(entry, jpool_entries); 1773 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, jpool_entries); 1774 1775 if (__predict_true(m != NULL)) 1776 pool_cache_put(mb_cache, m); 1777 splx(s); 1778 } 1779 1780 static int 1781 mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head, 1782 uint32_t *txidx) 1783 { 1784 struct mvgbe_tx_desc *f = NULL; 1785 struct mvgbe_txmap_entry *entry; 1786 bus_dma_segment_t *txseg; 1787 bus_dmamap_t txmap; 1788 uint32_t first, current, last, cmdsts; 1789 int m_csumflags, i; 1790 bool needs_defrag = false; 1791 1792 DPRINTFN(3, ("mvgbe_encap\n")); 1793 1794 entry = SIMPLEQ_FIRST(&sc->sc_txmap_head); 1795 if (entry == NULL) { 1796 DPRINTFN(2, ("mvgbe_encap: no txmap available\n")); 1797 return ENOBUFS; 1798 } 1799 txmap = entry->dmamap; 1800 1801 first = current = last = *txidx; 1802 1803 /* 1804 * Preserve m_pkthdr.csum_flags here since m_head might be 1805 * updated by m_defrag() 1806 */ 1807 m_csumflags = m_head->m_pkthdr.csum_flags; 1808 1809 do_defrag: 1810 if (__predict_false(needs_defrag == true)) { 1811 /* A small unaligned segment was detected. */ 1812 struct mbuf *m_new; 1813 m_new = m_defrag(m_head, M_DONTWAIT); 1814 if (m_new == NULL) { 1815 DPRINTFN(2, ("mvgbe_encap: defrag failed\n")); 1816 return EFBIG; 1817 } 1818 m_head = m_new; 1819 } 1820 1821 /* 1822 * Start packing the mbufs in this chain into 1823 * the fragment pointers. Stop when we run out 1824 * of fragments or hit the end of the mbuf chain. 1825 */ 1826 if (bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, BUS_DMA_NOWAIT)) { 1827 DPRINTFN(1, ("mvgbe_encap: dmamap failed\n")); 1828 return ENOBUFS; 1829 } 1830 1831 txseg = txmap->dm_segs; 1832 1833 if (__predict_true(needs_defrag == false)) { 1834 /* 1835 * Detect rarely encountered DMA limitation. 1836 */ 1837 for (i = 0; i < txmap->dm_nsegs; i++) { 1838 if (((txseg[i].ds_addr & 7) != 0) && 1839 (txseg[i].ds_len <= 8) && 1840 (txseg[i].ds_len >= 1) 1841 ) { 1842 txseg = NULL; 1843 bus_dmamap_unload(sc->sc_dmat, txmap); 1844 needs_defrag = true; 1845 goto do_defrag; 1846 } 1847 } 1848 } 1849 1850 /* Sync the DMA map. */ 1851 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1852 BUS_DMASYNC_PREWRITE); 1853 1854 if (sc->sc_cdata.mvgbe_tx_cnt + txmap->dm_nsegs >= 1855 MVGBE_TX_RING_CNT) { 1856 DPRINTFN(2, ("mvgbe_encap: too few descriptors free\n")); 1857 bus_dmamap_unload(sc->sc_dmat, txmap); 1858 return ENOBUFS; 1859 } 1860 1861 1862 DPRINTFN(3, ("mvgbe_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1863 1864 for (i = 0; i < txmap->dm_nsegs; i++) { 1865 f = &sc->sc_rdata->mvgbe_tx_ring[current]; 1866 f->bufptr = H2MVGBE32(txseg[i].ds_addr); 1867 f->bytecnt = H2MVGBE16(txseg[i].ds_len); 1868 if (i != 0) 1869 f->cmdsts = H2MVGBE32(MVGBE_BUFFER_OWNED_BY_DMA); 1870 last = current; 1871 current = MVGBE_TX_RING_NEXT(current); 1872 } 1873 1874 cmdsts = sc->sc_cmdsts_opts; 1875 if (m_csumflags & M_CSUM_IPv4) 1876 cmdsts |= MVGBE_TX_GENERATE_IP_CHKSUM; 1877 if (m_csumflags & M_CSUM_TCPv4) 1878 cmdsts |= 1879 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_TCP; 1880 if (m_csumflags & M_CSUM_UDPv4) 1881 cmdsts |= 1882 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_UDP; 1883 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1884 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t); 1885 1886 cmdsts |= MVGBE_TX_IP_NO_FRAG | 1887 MVGBE_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ 1888 } 1889 if (txmap->dm_nsegs == 1) 1890 f->cmdsts = H2MVGBE32(cmdsts | 1891 MVGBE_TX_ENABLE_INTERRUPT | 1892 MVGBE_TX_ZERO_PADDING | 1893 MVGBE_TX_FIRST_DESC | 1894 MVGBE_TX_LAST_DESC); 1895 else { 1896 f = &sc->sc_rdata->mvgbe_tx_ring[first]; 1897 f->cmdsts = H2MVGBE32(cmdsts | MVGBE_TX_FIRST_DESC); 1898 1899 f = &sc->sc_rdata->mvgbe_tx_ring[last]; 1900 f->cmdsts = H2MVGBE32( 1901 MVGBE_BUFFER_OWNED_BY_DMA | 1902 MVGBE_TX_ENABLE_INTERRUPT | 1903 MVGBE_TX_ZERO_PADDING | 1904 MVGBE_TX_LAST_DESC); 1905 1906 /* Sync descriptors except first */ 1907 MVGBE_CDTXSYNC(sc, 1908 (MVGBE_TX_RING_CNT - 1 == *txidx) ? 0 : (*txidx) + 1, 1909 txmap->dm_nsegs - 1, 1910 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1911 } 1912 1913 sc->sc_cdata.mvgbe_tx_chain[last].mvgbe_mbuf = m_head; 1914 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 1915 sc->sc_cdata.mvgbe_tx_map[last] = entry; 1916 1917 /* Finally, sync first descriptor */ 1918 sc->sc_rdata->mvgbe_tx_ring[first].cmdsts |= 1919 H2MVGBE32(MVGBE_BUFFER_OWNED_BY_DMA); 1920 MVGBE_CDTXSYNC(sc, *txidx, 1, 1921 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1922 1923 sc->sc_cdata.mvgbe_tx_cnt += i; 1924 *txidx = current; 1925 1926 DPRINTFN(3, ("mvgbe_encap: completed successfully\n")); 1927 1928 return 0; 1929 } 1930 1931 static void 1932 mvgbe_rxeof(struct mvgbe_softc *sc) 1933 { 1934 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1935 struct mvgbe_rx_desc *cur_rx; 1936 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1937 struct mbuf *m; 1938 bus_dmamap_t dmamap; 1939 uint32_t rxstat; 1940 uint16_t bufsize; 1941 int idx, cur, total_len; 1942 1943 idx = sc->sc_cdata.mvgbe_rx_prod; 1944 1945 DPRINTFN(3, ("mvgbe_rxeof %d\n", idx)); 1946 1947 for (;;) { 1948 cur = idx; 1949 1950 /* Sync the descriptor */ 1951 MVGBE_CDRXSYNC(sc, idx, 1952 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1953 1954 cur_rx = &sc->sc_rdata->mvgbe_rx_ring[idx]; 1955 1956 rxstat = MVGBE2H32(cur_rx->cmdsts); 1957 if ((rxstat & MVGBE_BUFFER_OWNED_MASK) == 1958 MVGBE_BUFFER_OWNED_BY_DMA) { 1959 /* Invalidate the descriptor -- it's not ready yet */ 1960 MVGBE_CDRXSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1961 sc->sc_cdata.mvgbe_rx_prod = idx; 1962 break; 1963 } 1964 #ifdef DIAGNOSTIC 1965 if ((rxstat & 1966 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) != 1967 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) 1968 panic( 1969 "mvgbe_rxeof: buffer size is smaller than packet"); 1970 #endif 1971 1972 dmamap = sc->sc_cdata.mvgbe_rx_jumbo_map; 1973 1974 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1975 BUS_DMASYNC_POSTREAD); 1976 1977 m = cdata->mvgbe_rx_chain[idx].mvgbe_mbuf; 1978 cdata->mvgbe_rx_chain[idx].mvgbe_mbuf = NULL; 1979 total_len = MVGBE2H16(cur_rx->bytecnt) - ETHER_CRC_LEN; 1980 bufsize = MVGBE2H16(cur_rx->bufsize); 1981 1982 cdata->mvgbe_rx_map[idx] = NULL; 1983 1984 idx = MVGBE_RX_RING_NEXT(idx); 1985 1986 if (rxstat & MVGBE_ERROR_SUMMARY) { 1987 #if 0 1988 int err = rxstat & MVGBE_RX_ERROR_CODE_MASK; 1989 1990 if (err == MVGBE_RX_CRC_ERROR) 1991 if_statinc(ifp, if_ierrors); 1992 if (err == MVGBE_RX_OVERRUN_ERROR) 1993 if_statinc(ifp, if_ierrors); 1994 if (err == MVGBE_RX_MAX_FRAME_LEN_ERROR) 1995 if_statinc(ifp, if_ierrors); 1996 if (err == MVGBE_RX_RESOURCE_ERROR) 1997 if_statinc(ifp, if_ierrors); 1998 #else 1999 if_statinc(ifp, if_ierrors); 2000 #endif 2001 mvgbe_newbuf(sc, cur, m, dmamap); 2002 continue; 2003 } 2004 2005 if (rxstat & MVGBE_RX_IP_FRAME_TYPE) { 2006 int flgs = 0; 2007 2008 /* Check IPv4 header checksum */ 2009 flgs |= M_CSUM_IPv4; 2010 if (!(rxstat & MVGBE_RX_IP_HEADER_OK)) 2011 flgs |= M_CSUM_IPv4_BAD; 2012 else if ((bufsize & MVGBE_RX_IP_FRAGMENT) == 0) { 2013 /* 2014 * Check TCPv4/UDPv4 checksum for 2015 * non-fragmented packet only. 2016 * 2017 * It seemd that sometimes 2018 * MVGBE_RX_L4_CHECKSUM_OK bit was set to 0 2019 * even if the checksum is correct and the 2020 * packet was not fragmented. So we don't set 2021 * M_CSUM_TCP_UDP_BAD even if csum bit is 0. 2022 */ 2023 2024 if (((rxstat & MVGBE_RX_L4_TYPE_MASK) == 2025 MVGBE_RX_L4_TYPE_TCP) && 2026 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0)) 2027 flgs |= M_CSUM_TCPv4; 2028 else if (((rxstat & MVGBE_RX_L4_TYPE_MASK) == 2029 MVGBE_RX_L4_TYPE_UDP) && 2030 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0)) 2031 flgs |= M_CSUM_UDPv4; 2032 } 2033 m->m_pkthdr.csum_flags = flgs; 2034 } 2035 2036 /* 2037 * Try to allocate a new jumbo buffer. If that 2038 * fails, copy the packet to mbufs and put the 2039 * jumbo buffer back in the ring so it can be 2040 * re-used. If allocating mbufs fails, then we 2041 * have to drop the packet. 2042 */ 2043 if (mvgbe_newbuf(sc, cur, NULL, dmamap) == ENOBUFS) { 2044 struct mbuf *m0; 2045 2046 m0 = m_devget(mtod(m, char *), total_len, 0, ifp); 2047 mvgbe_newbuf(sc, cur, m, dmamap); 2048 if (m0 == NULL) { 2049 aprint_error_ifnet(ifp, 2050 "no receive buffers available --" 2051 " packet dropped!\n"); 2052 if_statinc(ifp, if_ierrors); 2053 continue; 2054 } 2055 m = m0; 2056 } else { 2057 m_set_rcvif(m, ifp); 2058 m->m_pkthdr.len = m->m_len = total_len; 2059 } 2060 2061 /* Skip on first 2byte (HW header) */ 2062 m_adj(m, MVGBE_HWHEADER_SIZE); 2063 2064 /* pass it on. */ 2065 if_percpuq_enqueue(ifp->if_percpuq, m); 2066 } 2067 } 2068 2069 static void 2070 mvgbe_txeof(struct mvgbe_softc *sc) 2071 { 2072 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 2073 struct mvgbe_tx_desc *cur_tx; 2074 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2075 struct mvgbe_txmap_entry *entry; 2076 uint32_t txstat; 2077 int idx; 2078 2079 DPRINTFN(3, ("mvgbe_txeof\n")); 2080 2081 /* 2082 * Go through our tx ring and free mbufs for those 2083 * frames that have been sent. 2084 */ 2085 idx = cdata->mvgbe_tx_cons; 2086 while (idx != cdata->mvgbe_tx_prod) { 2087 MVGBE_CDTXSYNC(sc, idx, 1, 2088 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2089 2090 cur_tx = &sc->sc_rdata->mvgbe_tx_ring[idx]; 2091 #ifdef MVGBE_DEBUG 2092 if (mvgbe_debug >= 3) 2093 mvgbe_dump_txdesc(cur_tx, idx); 2094 #endif 2095 txstat = MVGBE2H32(cur_tx->cmdsts); 2096 if ((txstat & MVGBE_BUFFER_OWNED_MASK) == 2097 MVGBE_BUFFER_OWNED_BY_DMA) { 2098 MVGBE_CDTXSYNC(sc, idx, 1, BUS_DMASYNC_PREREAD); 2099 break; 2100 } 2101 if (txstat & MVGBE_TX_LAST_DESC) 2102 if_statinc(ifp, if_opackets); 2103 if (txstat & MVGBE_ERROR_SUMMARY) { 2104 int err = txstat & MVGBE_TX_ERROR_CODE_MASK; 2105 2106 if (err == MVGBE_TX_LATE_COLLISION_ERROR) 2107 if_statinc(ifp, if_collisions); 2108 if (err == MVGBE_TX_UNDERRUN_ERROR) 2109 if_statinc(ifp, if_oerrors); 2110 if (err == MVGBE_TX_EXCESSIVE_COLLISION_ERRO) 2111 if_statinc(ifp, if_collisions); 2112 } 2113 if (cdata->mvgbe_tx_chain[idx].mvgbe_mbuf != NULL) { 2114 entry = cdata->mvgbe_tx_map[idx]; 2115 2116 bus_dmamap_sync(sc->sc_dmat, entry->dmamap, 0, 2117 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2118 2119 bus_dmamap_unload(sc->sc_dmat, entry->dmamap); 2120 2121 m_freem(cdata->mvgbe_tx_chain[idx].mvgbe_mbuf); 2122 cdata->mvgbe_tx_chain[idx].mvgbe_mbuf = NULL; 2123 2124 SIMPLEQ_INSERT_TAIL(&sc->sc_txmap_head, entry, link); 2125 cdata->mvgbe_tx_map[idx] = NULL; 2126 } 2127 cdata->mvgbe_tx_cnt--; 2128 idx = MVGBE_TX_RING_NEXT(idx); 2129 } 2130 if (cdata->mvgbe_tx_cnt == 0) 2131 ifp->if_timer = 0; 2132 2133 if (cdata->mvgbe_tx_cnt < MVGBE_TX_RING_CNT - 2) 2134 ifp->if_flags &= ~IFF_OACTIVE; 2135 2136 cdata->mvgbe_tx_cons = idx; 2137 } 2138 2139 static uint8_t 2140 mvgbe_crc8(const uint8_t *data, size_t size) 2141 { 2142 int bit; 2143 uint8_t byte; 2144 uint8_t crc = 0; 2145 const uint8_t poly = 0x07; 2146 2147 while (size--) 2148 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 2149 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 2150 2151 return crc; 2152 } 2153 2154 CTASSERT(MVGBE_NDFSMT == MVGBE_NDFOMT); 2155 2156 static void 2157 mvgbe_filter_setup(struct mvgbe_softc *sc) 2158 { 2159 struct ethercom *ec = &sc->sc_ethercom; 2160 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 2161 struct ether_multi *enm; 2162 struct ether_multistep step; 2163 uint32_t dfut[MVGBE_NDFUT], dfsmt[MVGBE_NDFSMT], dfomt[MVGBE_NDFOMT]; 2164 uint32_t pxc; 2165 int i; 2166 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 2167 2168 memset(dfut, 0, sizeof(dfut)); 2169 memset(dfsmt, 0, sizeof(dfsmt)); 2170 memset(dfomt, 0, sizeof(dfomt)); 2171 2172 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 2173 goto allmulti; 2174 } 2175 2176 ETHER_LOCK(ec); 2177 ETHER_FIRST_MULTI(step, ec, enm); 2178 while (enm != NULL) { 2179 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2180 /* ranges are complex and somewhat rare */ 2181 ETHER_UNLOCK(ec); 2182 goto allmulti; 2183 } 2184 /* chip handles some IPv4 multicast specially */ 2185 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 2186 i = enm->enm_addrlo[5]; 2187 dfsmt[i>>2] |= 2188 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2189 } else { 2190 i = mvgbe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 2191 dfomt[i>>2] |= 2192 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2193 } 2194 2195 ETHER_NEXT_MULTI(step, enm); 2196 } 2197 ETHER_UNLOCK(ec); 2198 goto set; 2199 2200 allmulti: 2201 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 2202 for (i = 0; i < MVGBE_NDFSMT; i++) { 2203 dfsmt[i] = dfomt[i] = 2204 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2205 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2206 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2207 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2208 } 2209 } 2210 2211 set: 2212 pxc = MVGBE_READ(sc, MVGBE_PXC); 2213 pxc &= ~MVGBE_PXC_UPM; 2214 pxc |= MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP; 2215 if (ifp->if_flags & IFF_BROADCAST) { 2216 pxc &= ~(MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP); 2217 } 2218 if (ifp->if_flags & IFF_PROMISC) { 2219 pxc |= MVGBE_PXC_UPM; 2220 } 2221 MVGBE_WRITE(sc, MVGBE_PXC, pxc); 2222 2223 /* Set Destination Address Filter Unicast Table */ 2224 if (ifp->if_flags & IFF_PROMISC) { 2225 /* pass all unicast addresses */ 2226 for (i = 0; i < MVGBE_NDFUT; i++) { 2227 dfut[i] = 2228 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2229 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2230 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2231 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2232 } 2233 } else { 2234 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 2235 dfut[i>>2] = MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2236 } 2237 MVGBE_WRITE_FILTER(sc, MVGBE_DFUT, dfut, MVGBE_NDFUT); 2238 2239 /* Set Destination Address Filter Multicast Tables */ 2240 MVGBE_WRITE_FILTER(sc, MVGBE_DFSMT, dfsmt, MVGBE_NDFSMT); 2241 MVGBE_WRITE_FILTER(sc, MVGBE_DFOMT, dfomt, MVGBE_NDFOMT); 2242 } 2243 2244 #ifdef MVGBE_DEBUG 2245 static void 2246 mvgbe_dump_txdesc(struct mvgbe_tx_desc *desc, int idx) 2247 { 2248 #define DESC_PRINT(X) \ 2249 if (X) \ 2250 printf("txdesc[%d]." #X "=%#x\n", idx, X); 2251 2252 #ifdef MVGBE_BIG_ENDIAN 2253 DESC_PRINT(desc->bytecnt); 2254 DESC_PRINT(desc->l4ichk); 2255 DESC_PRINT(desc->cmdsts); 2256 DESC_PRINT(desc->nextdescptr); 2257 DESC_PRINT(desc->bufptr); 2258 #else 2259 DESC_PRINT(MVGBE2H32(desc->cmdsts)); 2260 DESC_PRINT(MVGBE2H16(desc->l4ichk)); 2261 DESC_PRINT(MVGBE2H16(desc->bytecnt)); 2262 DESC_PRINT(MVGBE2H32(desc->bufptr)); 2263 DESC_PRINT(MVGBE2H32(desc->nextdescptr)); 2264 #endif 2265 #undef DESC_PRINT 2266 } 2267 #endif 2268 2269 SYSCTL_SETUP(sysctl_mvgbe, "sysctl mvgbe subtree setup") 2270 { 2271 int rc; 2272 const struct sysctlnode *node; 2273 2274 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2275 0, CTLTYPE_NODE, "mvgbe", 2276 SYSCTL_DESCR("mvgbe interface controls"), 2277 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2278 goto err; 2279 } 2280 2281 mvgbe_root_num = node->sysctl_num; 2282 return; 2283 2284 err: 2285 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2286 } 2287 2288 static void 2289 sysctl_mvgbe_init(struct mvgbe_softc *sc) 2290 { 2291 const struct sysctlnode *node; 2292 int mvgbe_nodenum; 2293 2294 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2295 0, CTLTYPE_NODE, device_xname(sc->sc_dev), 2296 SYSCTL_DESCR("mvgbe per-controller controls"), 2297 NULL, 0, NULL, 0, CTL_HW, mvgbe_root_num, CTL_CREATE, 2298 CTL_EOL) != 0) { 2299 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 2300 return; 2301 } 2302 mvgbe_nodenum = node->sysctl_num; 2303 2304 /* interrupt moderation sysctls */ 2305 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2306 CTLFLAG_READWRITE, CTLTYPE_INT, "ipginttx", 2307 SYSCTL_DESCR("mvgbe TX interrupt moderation timer"), 2308 mvgbe_sysctl_ipginttx, 0, (void *)sc, 2309 0, CTL_HW, mvgbe_root_num, mvgbe_nodenum, CTL_CREATE, 2310 CTL_EOL) != 0) { 2311 aprint_normal_dev(sc->sc_dev, 2312 "couldn't create ipginttx sysctl node\n"); 2313 } 2314 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2315 CTLFLAG_READWRITE, CTLTYPE_INT, "ipgintrx", 2316 SYSCTL_DESCR("mvgbe RX interrupt moderation timer"), 2317 mvgbe_sysctl_ipgintrx, 0, (void *)sc, 2318 0, CTL_HW, mvgbe_root_num, mvgbe_nodenum, CTL_CREATE, 2319 CTL_EOL) != 0) { 2320 aprint_normal_dev(sc->sc_dev, 2321 "couldn't create ipginttx sysctl node\n"); 2322 } 2323 } 2324 2325 static int 2326 mvgbe_sysctl_ipginttx(SYSCTLFN_ARGS) 2327 { 2328 int error; 2329 unsigned int t; 2330 struct sysctlnode node; 2331 struct mvgbec_softc *csc; 2332 struct mvgbe_softc *sc; 2333 2334 node = *rnode; 2335 sc = node.sysctl_data; 2336 csc = device_private(device_parent(sc->sc_dev)); 2337 t = sc->sc_ipginttx; 2338 node.sysctl_data = &t; 2339 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2340 if (error || newp == NULL) 2341 return error; 2342 2343 if (mvgbe_ipginttx(csc, sc, t) < 0) 2344 return EINVAL; 2345 /* 2346 * update the softc with sysctl-changed value, and mark 2347 * for hardware update 2348 */ 2349 sc->sc_ipginttx = t; 2350 2351 return 0; 2352 } 2353 2354 static int 2355 mvgbe_sysctl_ipgintrx(SYSCTLFN_ARGS) 2356 { 2357 int error; 2358 unsigned int t; 2359 struct sysctlnode node; 2360 struct mvgbec_softc *csc; 2361 struct mvgbe_softc *sc; 2362 2363 node = *rnode; 2364 sc = node.sysctl_data; 2365 csc = device_private(device_parent(sc->sc_dev)); 2366 t = sc->sc_ipgintrx; 2367 node.sysctl_data = &t; 2368 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2369 if (error || newp == NULL) 2370 return error; 2371 2372 if (mvgbe_ipgintrx(csc, sc, t) < 0) 2373 return EINVAL; 2374 /* 2375 * update the softc with sysctl-changed value, and mark 2376 * for hardware update 2377 */ 2378 sc->sc_ipgintrx = t; 2379 2380 return 0; 2381 } 2382
Indexes created Tue Oct 07 21:09:53 GMT 2025