| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| v10_structs.h | 31 uint32_t reserved_0; // offset: 0 (0x0)
32 uint32_t reserved_1; // offset: 1 (0x1)
33 uint32_t reserved_2; // offset: 2 (0x2)
34 uint32_t reserved_3; // offset: 3 (0x3)
35 uint32_t reserved_4; // offset: 4 (0x4)
36 uint32_t reserved_5; // offset: 5 (0x5)
37 uint32_t reserved_6; // offset: 6 (0x6)
38 uint32_t reserved_7; // offset: 7 (0x7)
39 uint32_t reserved_8; // offset: 8 (0x8)
40 uint32_t reserved_9; // offset: 9 (0x9
[all...] |
| cik_structs.h | 30 uint32_t header;
31 uint32_t compute_dispatch_initiator;
32 uint32_t compute_dim_x;
33 uint32_t compute_dim_y;
34 uint32_t compute_dim_z;
35 uint32_t compute_start_x;
36 uint32_t compute_start_y;
37 uint32_t compute_start_z;
38 uint32_t compute_num_thread_x;
39 uint32_t compute_num_thread_y
[all...] |
| vi_structs.h | 30 uint32_t sdmax_rlcx_rb_cntl;
31 uint32_t sdmax_rlcx_rb_base;
32 uint32_t sdmax_rlcx_rb_base_hi;
33 uint32_t sdmax_rlcx_rb_rptr;
34 uint32_t sdmax_rlcx_rb_wptr;
35 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
36 uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
37 uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
38 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
39 uint32_t sdmax_rlcx_rb_rptr_addr_lo
[all...] |
| v9_structs.h | 30 uint32_t sdmax_rlcx_rb_cntl;
31 uint32_t sdmax_rlcx_rb_base;
32 uint32_t sdmax_rlcx_rb_base_hi;
33 uint32_t sdmax_rlcx_rb_rptr;
34 uint32_t sdmax_rlcx_rb_rptr_hi;
35 uint32_t sdmax_rlcx_rb_wptr;
36 uint32_t sdmax_rlcx_rb_wptr_hi;
37 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
38 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
39 uint32_t sdmax_rlcx_rb_rptr_addr_lo
[all...] |
| /src/sys/arch/ews4800mips/stand/common/ |
| common.h | 37 bool blk_to_2d_position(uint32_t, uint32_t *, int *);
38 bool blk_to_2hc_position(uint32_t, uint32_t *, int *);
39 bool blk_to_2hd_position(uint32_t, uint32_t *, int *);
|
| /src/sys/arch/amiga/stand/bootblock/elf2bb/ |
| chksum.h | 34 uint32_t chksum(uint32_t *, int);
|
| /src/sys/arch/x86/pci/ |
| amdsmn.h | 31 int amdsmn_read(device_t, uint32_t, uint32_t *);
32 int amdsmn_write(device_t, uint32_t, uint32_t);
|
| /src/sys/dev/dtv/ |
| dtv_math.h | 38 uint32_t dtv_intlog10(uint32_t);
|
| /src/sys/arch/arm/nxp/ |
| imx6_ocotpvar.h | 32 uint32_t imxocotp_read(uint32_t);
|
| /src/sys/arch/evbmips/include/ |
| uboot.h | 35 uint32_t gd_flags;
36 uint32_t gd_baudrate;
37 uint32_t gd_have_console;
38 uint32_t gd_memsize;
39 uint32_t gd_reloc_off;
40 uint32_t gd_env_addr;
41 uint32_t gd_env_valid;
46 uint32_t bd_baudrate;
47 uint32_t bd_ipaddr;
49 uint32_t bd_arch_number
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_socbb.h | 29 uint32_t state;
30 uint32_t dscclk_mhz;
31 uint32_t dcfclk_mhz;
32 uint32_t socclk_mhz;
33 uint32_t dram_speed_mts;
34 uint32_t fabricclk_mhz;
35 uint32_t dispclk_mhz;
36 uint32_t phyclk_mhz;
37 uint32_t dppclk_mhz;
41 uint32_t sr_exit_time_us
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| gpio_regs.h | 32 uint32_t MASK_reg;
33 uint32_t MASK_mask;
34 uint32_t MASK_shift;
35 uint32_t A_reg;
36 uint32_t A_mask;
37 uint32_t A_shift;
38 uint32_t EN_reg;
39 uint32_t EN_mask;
40 uint32_t EN_shift;
41 uint32_t Y_reg
[all...] |
| /src/sys/arch/sgimips/hpc/ |
| hpcvar.h | 42 uint32_t scsi0_regs;
43 uint32_t scsi0_regs_size;
44 uint32_t scsi0_cbp;
45 uint32_t scsi0_ndbp;
46 uint32_t scsi0_bc;
47 uint32_t scsi0_ctl;
48 uint32_t scsi0_gio;
49 uint32_t scsi0_dev;
50 uint32_t scsi0_dmacfg;
51 uint32_t scsi0_piocfg
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_pm4_headers.h | 34 uint32_t reserved1:8;
36 uint32_t opcode:8;
38 uint32_t count:14;
40 uint32_t type:2;
42 uint32_t u32all;
55 uint32_t ordinal1;
60 uint32_t pasid:16;
61 uint32_t reserved1:8;
62 uint32_t diq_enable:1;
63 uint32_t process_quantum:7
[all...] |
| /src/sys/arch/cats/include/ |
| cyclone_boot.h | 46 uint32_t bt_magic; /* boot info magic number */
47 uint32_t bt_vargp; /* virtual addr of arg page */
48 uint32_t bt_pargp; /* physical addr of arg page */
51 uint32_t bt_memstart; /* start of physical memory */
52 uint32_t bt_memend; /* end of physical memory */
53 uint32_t bt_memavail; /* start of avail phys memory */
54 uint32_t bt_fclk; /* fclk frequency */
55 uint32_t bt_pciclk; /* PCI bus frequency */
56 uint32_t bt_vers; /* structure version (CATS) */
57 uint32_t bt_features; /* feature mask (CATS) *
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/modules/color/ |
| luts_1d.h | 33 uint32_t custom_float_x;
34 uint32_t custom_float_y;
35 uint32_t custom_float_slope;
39 uint32_t red;
40 uint32_t green;
41 uint32_t blue;
42 uint32_t delta_red;
43 uint32_t delta_green;
44 uint32_t delta_blue;
51 uint32_t hw_points_num
[all...] |
| /src/usr.bin/cksum/ |
| crc_extern.h | 35 int crc(int, uint32_t *, off_t *);
36 uint32_t crc_buf(uint32_t, const void *, size_t);
37 uint32_t crc_byte(uint32_t, unsigned int);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| smu8.h | 34 uint32_t Version;
35 uint32_t ImageSize;
36 uint32_t CodeSize;
37 uint32_t HeaderSize;
38 uint32_t EntryPoint;
39 uint32_t Rtos;
40 uint32_t UcodeLoadStatus;
41 uint32_t DpmTable;
42 uint32_t FanTable;
43 uint32_t PmFuseTable
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| clock_source.h | 38 uint32_t percentage; /*> In unit of 0.01% or 0.001%*/
39 uint32_t percentage_divider; /*> 100 or 1000 */
40 uint32_t freq_range_khz;
41 uint32_t modulation_freq_hz;
47 uint32_t feedback_amount;
48 uint32_t nfrac_amount;
49 uint32_t ds_frac_size;
50 uint32_t ds_frac_amount;
59 uint32_t ENABLE_SS:1;
60 uint32_t DISPLAY_BLANKED:1
[all...] |
| /src/sys/netcan/ |
| can_link.h | 41 uint32_t cltc_prop_min; /* prop seg, in tq */
42 uint32_t cltc_prop_max;
43 uint32_t cltc_ps1_min; /* phase1 seg, in tq */
44 uint32_t cltc_ps1_max;
45 uint32_t cltc_ps2_min; /* phase 2 seg, in tq */
46 uint32_t cltc_ps2_max;
47 uint32_t cltc_sjw_max; /* Synchronisation Jump Width */
48 uint32_t cltc_brp_min; /* bit-rate prescaler */
49 uint32_t cltc_brp_max;
50 uint32_t cltc_brp_inc
[all...] |
| /src/sys/arch/mips/include/ |
| kcore.h | 40 uint32_t sysmapsize; /* size of Sysmap */
41 uint32_t archlevel; /* MIPS architecture level */
42 uint32_t pg_shift; /* PTE page frame num shift */
43 uint32_t pg_frame; /* PTE page frame num mask */
44 uint32_t pg_v; /* PTE valid bit */
45 uint32_t nmemsegs; /* Number of RAM segments */
|
| /src/sys/sys/ |
| disklabel_rdb.h | 42 #define RDBNULL ((uint32_t)0xffffffff)
50 uint32_t id; /* 'RDSK' */
51 uint32_t nsumlong; /* number of long words in check sum */
52 uint32_t chksum; /* simple additive with wrap checksum */
53 uint32_t hostid; /* scsi target of host */
54 uint32_t nbytes; /* size of disk blocks */
55 uint32_t flags;
56 uint32_t badbhead; /* linked list of badblocks */
57 uint32_t partbhead; /* linked list of partblocks */
58 uint32_t fsbhead; /* " " of fsblocks *
[all...] |
| /src/sys/arch/sgimips/include/ |
| sysconf.h | 78 void (*intr0)(vaddr_t, uint32_t, uint32_t);
79 void (*intr1)(vaddr_t, uint32_t, uint32_t);
80 void (*intr2)(vaddr_t, uint32_t, uint32_t);
81 void (*intr3)(vaddr_t, uint32_t, uint32_t);
82 void (*intr4)(vaddr_t, uint32_t, uint32_t);
[all...] |
| /src/sys/arch/arc/dti/ |
| btlvar.h | 36 uint32_t (*bc_kvtophys)(uint32_t);
37 uint32_t (*bc_phystokv)(uint32_t);
|
| /src/sys/arch/powerpc/ibm4xx/dev/ |
| malvar.h | 31 int mal_start(int, uint32_t, uint32_t);
|
