| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_uvd_v4_2.c | 41 * Let the UVD memory controller know it's offsets
51 if (rdev->uvd.fw_header_present)
52 addr = (rdev->uvd.gpu_addr + 0x200) >> 3;
54 addr = rdev->uvd.gpu_addr >> 3;
67 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;
72 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
76 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
79 if (rdev->uvd.fw_header_present)
80 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles);
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| radeon_uvd.c | 79 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
144 rdev->uvd.fw_header_present = false;
145 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES;
160 rdev->uvd.fw_header_present = true;
165 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
169 * Limit the number of UVD handles depending on
173 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES;
193 RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles;
196 NULL, &rdev->uvd.vcpu_bo);
198 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r)
[all...] |
| radeon_uvd_v2_2.c | 75 * Emit a semaphore command (either wait or signal) to the UVD ring.
101 * Let the UVD memory controller know it's offsets
118 addr = rdev->uvd.gpu_addr >> 3;
130 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;
135 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
139 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
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| radeon_uvd_v1_0.c | 113 * Let the UVD memory controller know it's offsets
126 addr = (rdev->uvd.gpu_addr >> 3) + 16;
138 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;
143 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
147 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
150 WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr));
156 * uvd_v1_0_init - start and test UVD block
187 DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r);
240 DRM_INFO("UVD initialized successfully.\n");
251 * Stop the UVD block, mark ring as not ready any mor
[all...] |
| radeon_drv.c | 312 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
313 module_param_named(uvd, radeon_uvd, int, 0444);
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| radeon_fence.c | 902 rdev->fence_drv[ring].cpu_addr = (uint32_t *)((uint8_t *)rdev->uvd.cpu_addr + index);
903 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
1113 case R600_RING_TYPE_UVD_INDEX: return "radeon.uvd";
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| radeon.h | 1384 /* UVD clocks */
1591 /* default uvd power state */
1627 /* track UVD streams */
1707 * UVD
2395 /* protects concurrent UVD register access */
2447 struct radeon_uvd uvd; member in struct:radeon_device
2467 const struct firmware *uvd_fw; /* UVD firmware */
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_uvd.c | 45 #include "uvd/uvd_4_2_d.h"
93 * Used for emulating virtual memory support on UVD 4.2.
139 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
196 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
203 r = amdgpu_ucode_validate(adev->uvd.fw);
207 release_firmware(adev->uvd.fw);
208 adev->uvd.fw = NULL;
212 /* Set the default UVD handles that the firmware can handle */
213 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
215 hdr = (const struct common_firmware_header *)adev->uvd.fw->data
[all...] |
| amdgpu_uvd_v7_0.c | 38 #include "uvd/uvd_7_0_offset.h"
39 #include "uvd/uvd_7_0_sh_mask.h"
47 #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h"
82 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
96 if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
97 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
99 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
113 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
130 if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
131 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR)
[all...] |
| amdgpu_uvd_v6_0.c | 35 #include "uvd/uvd_6_0_d.h"
36 #include "uvd/uvd_6_0_sh_mask.h"
72 (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16));
100 if (ring == &adev->uvd.inst->ring_enc[0])
130 if (ring == &adev->uvd.inst->ring_enc[0])
161 if (ring == &adev->uvd.inst->ring_enc[0])
170 * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working
204 * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg
266 * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy ms
[all...] |
| amdgpu_uvd_v4_2.c | 36 #include "uvd/uvd_4_2_d.h"
37 #include "uvd/uvd_4_2_sh_mask.h"
101 adev->uvd.num_uvd_inst = 1;
115 /* UVD TRAP */
116 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
124 ring = &adev->uvd.inst->ring;
125 snprintf(ring->name, sizeof ring->name, "uvd");
126 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
154 * uvd_v4_2_hw_init - start and test UVD block
163 struct amdgpu_ring *ring = &adev->uvd.inst->ring
[all...] |
| amdgpu_uvd_v5_0.c | 36 #include "uvd/uvd_5_0_d.h"
37 #include "uvd/uvd_5_0_sh_mask.h"
99 adev->uvd.num_uvd_inst = 1;
113 /* UVD TRAP */
114 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
122 ring = &adev->uvd.inst->ring;
123 snprintf(ring->name, sizeof(ring->name), "uvd");
124 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
150 * uvd_v5_0_hw_init - start and test UVD block
159 struct amdgpu_ring *ring = &adev->uvd.inst->ring
[all...] |
| amdgpu_uvd.h | 39 (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \
57 const struct firmware *fw; /* UVD firmware */
|
| amdgpu_kms.c | 226 fw_info->ver = adev->uvd.fw_version;
358 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
359 if (adev->uvd.harvest_config & (1 << i))
362 if (adev->uvd.inst[i].ring.sched.ready)
378 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
379 if (adev->uvd.harvest_config & (1 << i))
382 for (j = 0; j < adev->uvd.num_enc_rings; j++)
383 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
392 if (adev->uvd.harvest_config & (1 << i))
404 if (adev->uvd.harvest_config & (1 << i)
[all...] |
| amdgpu_fence.c | 413 index = ALIGN(adev->uvd.fw->size, 8);
414 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
415 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
|
| amdgpu_ctx.c | 102 sched = &adev->uvd.inst[0].ring.sched;
112 sched = &adev->uvd.inst[0].ring_enc[0].sched;
|
| amdgpu_ucode.c | 402 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
612 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
|
| amdgpu.h | 798 /* protects concurrent UVD register access */
906 /* uvd */
907 struct amdgpu_uvd uvd; member in struct:amdgpu_device
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| amdgpu_pm.c | 3183 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
3186 /* enable/disable Low Memory PState for UVD (4k videos) */
3188 adev->uvd.decode_image_width >= WIDTH_4K) {
3601 /* UVD clocks */
3604 seq_printf(m, "UVD: Disabled\n");
3606 seq_printf(m, "UVD: Enabled\n");
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| smu10_hwmgr.h | 114 uint32_t uvd : 1; member in struct:pp_disable_nbpslo_flags::__anon67c21e05010a::__anon67c21e050208
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| smu8_hwmgr.h | 137 uint32_t uvd : 1; member in struct:pp_disable_nb_ps_flags::__anonaf84f57c010a::__anonaf84f57c0208
|
