| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_vcn_v2_5.c | 39 #include "vcn/vcn_2_5_offset.h"
40 #include "vcn/vcn_2_5_sh_mask.h"
41 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
88 adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS;
89 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
92 adev->vcn.harvest_config |= 1 << i;
95 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
100 adev->vcn.num_vcn_inst = 1;
103 adev->vcn.num_vcn_inst = 2;
104 adev->vcn.harvest_config = 0
[all...] |
| amdgpu_vcn.c | 70 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
85 adev->vcn.indirect_sram = true;
91 adev->vcn.indirect_sram = true;
97 adev->vcn.indirect_sram = true;
103 adev->vcn.indirect_sram = true;
109 adev->vcn.indirect_sram = true;
115 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
122 r = amdgpu_ucode_validate(adev->vcn.fw);
126 release_firmware(adev->vcn.fw);
127 adev->vcn.fw = NULL
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| amdgpu_vcn_v2_0.c | 38 #include "vcn/vcn_2_0_0_offset.h"
39 #include "vcn/vcn_2_0_0_sh_mask.h"
40 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
76 adev->vcn.num_vcn_inst = 1;
77 adev->vcn.num_enc_rings = 2;
87 * vcn_v2_0_sw_init - sw init for VCN block
99 /* VCN DEC TRAP */
102 &adev->vcn.inst->irq);
106 /* VCN ENC TRAP */
107 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
[all...] |
| amdgpu_vcn_v1_0.c | 38 #include "vcn/vcn_1_0_offset.h"
39 #include "vcn/vcn_1_0_sh_mask.h"
44 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
75 adev->vcn.num_vcn_inst = 1;
76 adev->vcn.num_enc_rings = 2;
88 * vcn_v1_0_sw_init - sw init for VCN block
100 /* VCN DEC TRAP */
102 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
106 /* VCN ENC TRAP */
107 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
[all...] |
| amdgpu_vega10_reg_init.c | 88 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_DOORBELL64_VCN0_1;
89 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_DOORBELL64_VCN2_3;
90 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_DOORBELL64_VCN4_5;
91 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_DOORBELL64_VCN6_7;
|
| amdgpu_ctx.c | 117 scheds = adev->vcn.vcn_dec_sched;
118 num_scheds = adev->vcn.num_vcn_dec_sched;
121 scheds = adev->vcn.vcn_enc_sched;
122 num_scheds = adev->vcn.num_vcn_enc_sched;
661 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
662 if (adev->vcn.harvest_config & (1 << i))
664 adev->vcn.vcn_dec_sched[adev->vcn.num_vcn_dec_sched++] =
665 &adev->vcn.inst[i].ring_dec.sched;
668 for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
[all...] |
| amdgpu_vega20_reg_init.c | 94 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_VEGA20_DOORBELL64_VCN0_1;
95 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCN2_3;
96 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCN4_5;
97 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCN6_7;
|
| amdgpu_vcn.h | 116 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
120 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \
126 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA, value); \
127 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
132 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = offset; \
133 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = value; \
193 const struct firmware *fw; /* VCN firmware */
|
| amdgpu_jpeg_v2_5.c | 35 #include "vcn/vcn_2_5_offset.h"
36 #include "vcn/vcn_2_5_sh_mask.h"
37 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
124 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i;
176 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i);
|
| amdgpu_doorbell.h | 70 } vcn; member in union:amdgpu_doorbell_index::__anone9660ee2010a
139 * overlap the doorbell assignment with VCN as they are mutually exclusive
140 * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD
193 * overlap the doorbell assignment with VCN as they are mutually exclusive
264 /* VCN engine use 32 bits doorbell */
270 /* overlap the doorbell assignment with VCN as they are mutually exclusive
|
| amdgpu_nv.c | 615 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
616 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
617 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
618 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
660 /* TODO: will add them during VCN v2 implementation */
|
| amdgpu_kms.c | 230 fw_info->ver = adev->vcn.fw_version;
391 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
395 if (adev->vcn.inst[i].ring_dec.sched.ready)
403 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
407 for (j = 0; j < adev->vcn.num_enc_rings; j++)
408 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
1400 /* VCN */
1405 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
|
| amdgpu_jpeg_v2_0.c | 35 #include "vcn/vcn_2_0_0_offset.h"
36 #include "vcn/vcn_2_0_0_sh_mask.h"
37 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
112 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
158 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
|
| amdgpu_ucode.c | 420 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
|
| amdgpu.h | 912 /* vcn */
913 struct amdgpu_vcn vcn; member in struct:amdgpu_device
|
| /src/sys/fs/ntfs/ |
| ntfs_subr.c | 113 cn_t vcn)
132 ddprintf(("%s: type: 0x%x, vcn: %qu - %qu\n", __func__,
136 (vap->va_vcnstart <= vcn) && (vap->va_vcnend >= vcn) &&
158 const char *name, cn_t vcn, struct ntvattr **vapp)
171 dprintf(("%s: ino: %llu, type: 0x%x, name: %s, vcn: %qu\n",
173 (long long)vcn));
176 dprintf(("%s: ino: %llu, type: 0x%x, vcn: %qu\n", __func__,
177 (unsigned long long)ip->i_number, type, (long long)vcn));
182 error = ntfs_findvattr(ntmp, ip, &lvap, vapp, type, name, namelen, vcn);
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