| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_dpp_dscl.c | 473 bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps)
476 return vtaps <= (num_partitions - ceil_vratio + 2);
478 return vtaps <= num_partitions;
486 int vtaps = scl_data->taps.v_taps; local in function:dpp1_dscl_find_lb_memory_config
498 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
505 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
514 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
522 /*Ensure we can support the requested number of vtaps*/
523 ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
731 /* HTaps/VTaps */
[all...] |
| dcn10_dpp.h | 1389 int vtaps);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| display_mode_structs.h | 307 unsigned int vtaps; member in struct:_vcs_dpi_scaler_taps_st
|
| amdgpu_display_mode_vba.c | 422 mode_lib->vba.vtaps[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps;
|
| display_mode_vba.h | 286 unsigned int vtaps[DC__NUM_DPP__MAX]; member in struct:vba_vars_st
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_mode_vba_21.c | 168 double vtaps,
326 unsigned int vtaps[],
1214 double vtaps,
1225 *VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1);
1227 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
1520 mode_lib->vba.vtaps[k] / 6.0
1530 if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
1867 mode_lib->vba.vtaps[k],
2452 mode_lib->vba.vtaps,
3418 || mode_lib->vba.vtaps[k] != 1.0))
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_mode_vba_20.c | 130 double vtaps,
820 double vtaps,
831 *VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1);
833 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
1141 mode_lib->vba.vtaps[k] / 6.0
1151 if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
1901 mode_lib->vba.vtaps[k],
2427 1)) - (mode_lib->vba.vtaps[k] - 1);
3313 || mode_lib->vba.vtaps[k] != 1.0)) {
3315 } else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.
[all...] |
| amdgpu_display_mode_vba_20v2.c | 154 double vtaps,
880 double vtaps,
891 *VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1);
893 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
1201 mode_lib->vba.vtaps[k] / 6.0
1211 if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
1937 mode_lib->vba.vtaps[k],
2461 1)) - (mode_lib->vba.vtaps[k] - 1);
3350 || mode_lib->vba.vtaps[k] != 1.0)) {
3352 } else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calc_auto.c | 104 v->vtaps[k] = v->override_vta_ps[k];
107 v->vtaps[k] = v->acceptable_quality_vta_ps;
137 if (v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio || v->h_ratio[k] > v->htaps[k] || v->v_ratio[k] > v->vtaps[k] || (v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16 && (v->h_ratio[k] / 2.0 > v->hta_pschroma[k] || v->v_ratio[k] / 2.0 > v->vta_pschroma[k]))) {
336 v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], 1.0);
345 v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max5(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_factor_chroma[k], 1.0);
432 v->number_of_dpp_required_for_lb_size =dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0);
435 v->number_of_dpp_required_for_lb_size =dcn_bw_max2(dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0),dcn_bw_ceil2((v->vta_pschroma[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k] / 2.0, 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0));
559 v->effective_lb_latency_hiding_source_lines_luma =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0);
752 v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0;
764 v->v_init_c = (v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0
[all...] |
| amdgpu_dcn_calcs.c | 395 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| dcn_calcs.h | 205 float vtaps[number_of_planes_minus_one + 1]; member in struct:dcn_bw_internal_vars
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 713 u32 vtaps; /* vertical scaler taps */ member in struct:dce10_wm_params
916 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
917 (wm->vtaps >= 5) ||
1006 if (lb_partitions <= (wm->vtaps + 1))
1068 wm_high.vtaps = 1;
1070 wm_high.vtaps = 2;
1107 wm_low.vtaps = 1;
1109 wm_low.vtaps = 2;
|
| amdgpu_dce_v11_0.c | 739 u32 vtaps; /* vertical scaler taps */ member in struct:dce10_wm_params
942 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
943 (wm->vtaps >= 5) ||
1032 if (lb_partitions <= (wm->vtaps + 1))
1094 wm_high.vtaps = 1;
1096 wm_high.vtaps = 2;
1133 wm_low.vtaps = 1;
1135 wm_low.vtaps = 2;
|
| amdgpu_dce_v6_0.c | 511 u32 vtaps; /* vertical scaler taps */ member in struct:dce6_wm_params
714 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
715 (wm->vtaps >= 5) ||
804 if (lb_partitions <= (wm->vtaps + 1))
875 wm_high.vtaps = 1;
877 wm_high.vtaps = 2;
902 wm_low.vtaps = 1;
904 wm_low.vtaps = 2;
|
| amdgpu_dce_v8_0.c | 648 u32 vtaps; /* vertical scaler taps */ member in struct:dce8_wm_params
851 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
852 (wm->vtaps >= 5) ||
941 if (lb_partitions <= (wm->vtaps + 1))
1003 wm_high.vtaps = 1;
1005 wm_high.vtaps = 2;
1042 wm_low.vtaps = 1;
1044 wm_low.vtaps = 2;
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_evergreen.c | 1949 u32 vtaps; /* vertical scaler taps */ member in struct:evergreen_wm_params
2086 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
2087 (wm->vtaps >= 5) ||
2143 if (lb_partitions <= (wm->vtaps + 1))
2203 wm_high.vtaps = 1;
2205 wm_high.vtaps = 2;
2230 wm_low.vtaps = 1;
2232 wm_low.vtaps = 2;
|
| radeon_si.c | 2077 u32 vtaps; /* vertical scaler taps */ member in struct:dce6_wm_params
2232 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
2233 (wm->vtaps >= 5) ||
2291 if (lb_partitions <= (wm->vtaps + 1))
2354 wm_high.vtaps = 1;
2356 wm_high.vtaps = 2;
2381 wm_low.vtaps = 1;
2383 wm_low.vtaps = 2;
|
| radeon_cik.c | 8994 u32 vtaps; /* vertical scaler taps */ member in struct:dce8_wm_params
9197 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
9198 (wm->vtaps >= 5) ||
9287 if (lb_partitions <= (wm->vtaps + 1))
9350 wm_high.vtaps = 1;
9352 wm_high.vtaps = 2;
9390 wm_low.vtaps = 1;
9392 wm_low.vtaps = 2;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 2094 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2159 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
|
