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    Searched refs:wb_info (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_stream.c 373 struct dc_writeback_info *wb_info)
384 if (wb_info == NULL) {
389 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {
394 wb_info->dwb_params.out_transfer_func = stream->out_transfer_func;
396 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
404 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) {
405 stream->writeback_info[i] = *wb_info;
411 stream->writeback_info[stream->num_wb_info++] = *wb_info;
416 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
427 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
hw_sequencer.h 154 struct dc_writeback_info *wb_info,
157 struct dc_writeback_info *wb_info,
164 struct dc_writeback_info *wb_info);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
dcn20_hwseq.h 109 struct dc_writeback_info *wb_info,
amdgpu_dcn20_hwseq.c 1754 struct dc_writeback_info *wb_info,
1761 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1762 ASSERT(wb_info->wb_enabled);
1763 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1764 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1768 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1770 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
1771 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
1775 dwb->funcs->enable(dwb, &wb_info->dwb_params)
    [all...]
amdgpu_dcn20_resource.c 1838 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; local in function:dcn20_populate_dml_writeback_from_context
1844 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1846 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1847 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1848 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1849 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1852 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1853 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1856 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1857 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_stream.h 348 struct dc_writeback_info *wb_info);
356 struct dc_writeback_info *wb_info);

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