| /src/sys/dev/pci/igma/ |
| igmafb.c | 422 co->write_reg(cd, sc->sc_chip.vga_cntrl, r | VGA_CNTRL_DISABLE);
428 co->write_reg(cd, PF_WINPOS(pipe),
430 co->write_reg(cd, PF_WINSZ(pipe),
434 co->write_reg(cd, PIPE_SRCSZ(pipe),
438 co->write_reg(cd, PIPE_CONF(pipe),
445 co->write_reg(cd, PRI_CTRL(pipe), r | cd->pri_cntrl);
446 co->write_reg(cd, PRI_LINOFF(pipe), 0);
447 co->write_reg(cd, PRI_STRIDE(pipe), sc->sc_stride);
448 co->write_reg(cd, PRI_SURF(pipe), 0);
449 co->write_reg(cd, PRI_TILEOFF(pipe), 0)
[all...] |
| /src/sys/dev/pci/ |
| igmavar.h | 29 void (*write_reg)(const struct igma_chip *, int, u_int32_t); member in struct:igma_chip_ops
|
| igma.c | 539 co->write_reg(cd, ii->ii_reg, reg);
|
| /src/sys/dev/pci/igc/ |
| igc_phy.c | 41 phy->ops.write_reg = igc_null_write_reg;
440 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
447 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
451 ret_val = phy->ops.write_reg(hw,
503 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
763 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
783 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
874 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
878 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
882 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA
[all...] |
| igc_hw.h | 240 int (*write_reg)(struct igc_hw *, uint32_t, uint16_t); member in struct:igc_phy_operations
|
| igc_i225.c | 158 phy->ops.write_reg = igc_write_phy_reg_gpy;
|
| /src/sys/dev/ic/ |
| bmx280var.h | 56 int (*write_reg)(struct bmx280_sc *, uint8_t *, size_t); member in struct:bmx280_accessfuncs
|
| bmx280.c | 443 error = sc->sc_funcs->write_reg(sc, buf, 2);
700 error = sc->sc_funcs->write_reg(sc, cr, s);
|
| /src/sys/dev/spi/ |
| bmx280thpspi.c | 143 .write_reg = bmx280thpspi_write_reg,
|
| /src/sys/dev/podulebus/ |
| esp_podule.c | 100 void (*write_reg)(struct ncr53c9x_softc *, int, uint8_t); member in struct:__anon32a2576c0108
141 esc->sc_esp_glue.gl_write_reg = devices[i].write_reg;
|
| /src/sys/dev/pci/ixgbe/ |
| ixgbe_phy.c | 265 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
529 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
813 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
842 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
857 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
869 hw->phy.ops.write_reg(hw, MDIO_PMAPMD_CTRL1,MDIO_MMD_PMAPMD,
878 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
891 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1083 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1098 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG
[all...] |
| ixgbe_x550.c | 611 hw->phy.ops.write_reg = NULL;
2253 status = hw->phy.ops.write_reg(hw,
2272 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2290 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2307 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2473 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2484 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2518 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2523 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2534 phy->ops.write_reg = ixgbe_write_phy_reg_x550em
[all...] |
| ixgbe_api.c | 559 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
|
| ixgbe_type.h | 4135 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); member in struct:ixgbe_phy_operations
|
| ixgbe_common.c | 378 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
|
| /src/sys/dev/usb/ |
| uchcom.c | 446 write_reg(struct uchcom_softc *sc, function in typeref:typename:usbd_status
509 return write_reg(sc, UCHCOM_REG_STAT1, val, UCHCOM_REG_STAT1, val);
608 err = write_reg(sc, UCHCOM_REG_BREAK, brk, UCHCOM_REG_LCR, lcr);
684 if ((err = write_reg(sc,
736 err = write_reg(sc, UCHCOM_REG_LCR, lcr, UCHCOM_REG_LCR2, lcr2);
|
| /src/sys/dev/i2c/ |
| bmx280thpi2c.c | 141 .write_reg = bmx280thpi2c_write_register,
|
