HomeSort by: relevance | last modified time | path
    Searched refs:x105 (Results 1 - 25 of 30) sorted by relevancy

1 2

  /src/sys/external/gpl2/dts/dist/include/dt-bindings/reset/
hisi,hi6220-resets.h 20 #define PERIPH_RSTDIS1_DIGACODEC 0x105
  /src/sys/arch/sparc64/include/
trap.h 115 #define T_RANGECHECK 0x105 /* ? */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pcie.dtsi 30 <0x105 &gic_its 0x2280 0x1>, /* PF5 */
  /src/sys/dev/isa/
gusreg.h 84 #define GUS_DATA_HIGH (0x105-GUS_IOH2_OFFSET)
  /src/tests/lib/libcurses/tests/
std_defines 42 assign KEY_RIGHT 0x105
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/cavium/
thunder-88xx.dtsi 194 reg = <0x0 0x105>;
  /src/lib/libcurses/
keyname.c 129 if (key == 0x105) {
curses.h 104 #define KEY_RIGHT 0x105 /* right arrow*/
  /src/lib/libform/
form.h 82 #define REQ_NEXT_FIELD (KEY_MAX + 0x105) /* move to the next field */
  /src/sys/dev/mii/
micphy.c 154 #define REG_RGMII_RX_DATA 0x105
  /src/sys/arch/hppa/dev/
cpudevs.h 44 #define HPPA_BOARD_HP852 0x105
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
fiji_ppsmc.h 186 #define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105)
smu7_ppsmc.h 183 #define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105)
tonga_ppsmc.h 207 #define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105)
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/
linux-event-codes.h 350 #define BTN_5 0x105
  /src/sys/arch/riscv/include/
insn.h 727 #define CSR_STVEC 0x105
  /src/sys/external/bsd/drm2/dist/include/drm/
drm_dp_helper.h 450 #define DP_TRAINING_LANE2_SET 0x105
  /src/lib/libintl/
plural_parser.c 57 #define T_ADDITIVE 0x105 /* + or - */
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
bif_5_0_d.h 407 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x105
  /src/sys/dev/usb/
if_otus.c 225 0x0ff, 0x100, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109,
2495 otus_write(sc, AR_MAC_REG_BACKOFF_PROTECT, 0x105);
2813 tmp = IEEE80211_IS_CHAN_2GHZ(c) ? 0x105 : 0x104;
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_8_1_enum.h 389 CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x105,
1052 DB_PERF_SEL_SX_DB_quad_slow_format = 0x105,
1607 SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x105,
2564 SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x105,
3570 #define SQ_DPP_ROW_SL5 0x105
gfx_8_0_enum.h 389 CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x105,
1589 SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x105,
2546 SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x105,
3552 #define SQ_DPP_ROW_SL5 0x105
  /src/sys/dev/qbus/
qfont.c 91 ,0x103 ,0x104 ,0x105 ,0x00 ,0x00 ,0x00 ,0x00 ,0x00 /* 88 */
126 ,0x103 ,0x104 ,0x105 ,0x00 ,0x00 ,0x00 ,0x00 ,0x00 /* 88 */
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
gmc_7_1_d.h 1162 #define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x105
gmc_8_1_d.h 1266 #define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x105

Completed in 199 milliseconds

1 2