1 /* $NetBSD: fiji_ppsmc.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 27 #ifndef _FIJI_PP_SMC_H_ 28 #define _FIJI_PP_SMC_H_ 29 30 #pragma pack(push, 1) 31 32 #define PPSMC_SWSTATE_FLAG_DC 0x01 33 #define PPSMC_SWSTATE_FLAG_UVD 0x02 34 #define PPSMC_SWSTATE_FLAG_VCE 0x04 35 36 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 37 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 38 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff 39 40 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 41 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 42 #define PPSMC_SYSTEMFLAG_GDDR5 0x04 43 44 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 45 46 #define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 47 #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 48 49 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 50 #define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 51 52 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 53 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 54 55 /* Defines for DPM 2.0 */ 56 #define PPSMC_DPM2FLAGS_TDPCLMP 0x01 57 #define PPSMC_DPM2FLAGS_PWRSHFT 0x02 58 #define PPSMC_DPM2FLAGS_OCP 0x04 59 60 /* Defines for display watermark level */ 61 #define PPSMC_DISPLAY_WATERMARK_LOW 0 62 #define PPSMC_DISPLAY_WATERMARK_HIGH 1 63 64 /* In the HW performance level's state flags: */ 65 #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 66 #define PPSMC_STATEFLAG_POWERBOOST 0x02 67 #define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04 68 #define PPSMC_STATEFLAG_POWERSHIFT 0x08 69 #define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10 70 #define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 71 #define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 72 73 /* Fan control algorithm: */ 74 #define FDO_MODE_HARDWARE 0 75 #define FDO_MODE_PIECE_WISE_LINEAR 1 76 77 enum FAN_CONTROL { 78 FAN_CONTROL_FUZZY, 79 FAN_CONTROL_TABLE 80 }; 81 82 /* Gemini Modes*/ 83 #define PPSMC_GeminiModeNone 0 /*Single GPU board*/ 84 #define PPSMC_GeminiModeMaster 1 /*Master GPU on a Gemini board*/ 85 #define PPSMC_GeminiModeSlave 2 /*Slave GPU on a Gemini board*/ 86 87 88 /* Return codes for driver to SMC communication. */ 89 #define PPSMC_Result_OK ((uint16_t)0x01) 90 #define PPSMC_Result_NoMore ((uint16_t)0x02) 91 92 #define PPSMC_Result_NotNow ((uint16_t)0x03) 93 94 #define PPSMC_Result_Failed ((uint16_t)0xFF) 95 #define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) 96 #define PPSMC_Result_UnknownVT ((uint16_t)0xFD) 97 98 #define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) 99 100 101 #define PPSMC_MSG_Halt ((uint16_t)0x10) 102 #define PPSMC_MSG_Resume ((uint16_t)0x11) 103 #define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12) 104 #define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13) 105 #define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14) 106 #define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15) 107 #define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16) 108 #define PPSMC_MSG_RunningOnAC ((uint16_t)0x17) 109 #define PPSMC_MSG_LevelUp ((uint16_t)0x18) 110 #define PPSMC_MSG_LevelDown ((uint16_t)0x19) 111 #define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a) 112 #define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20) 113 114 #define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f) 115 #define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40) 116 #define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41) 117 #define PPSMC_MSG_ForceHigh ((uint16_t)0x42) 118 #define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43) 119 120 #define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51) 121 #define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52) 122 #define PPSMC_MSG_EnableCac ((uint16_t)0x53) 123 #define PPSMC_MSG_DisableCac ((uint16_t)0x54) 124 #define PPSMC_DPMStateHistoryStart ((uint16_t)0x55) 125 #define PPSMC_DPMStateHistoryStop ((uint16_t)0x56) 126 #define PPSMC_CACHistoryStart ((uint16_t)0x57) 127 #define PPSMC_CACHistoryStop ((uint16_t)0x58) 128 #define PPSMC_TDPClampingActive ((uint16_t)0x59) 129 #define PPSMC_TDPClampingInactive ((uint16_t)0x5A) 130 #define PPSMC_StartFanControl ((uint16_t)0x5B) 131 #define PPSMC_StopFanControl ((uint16_t)0x5C) 132 #define PPSMC_NoDisplay ((uint16_t)0x5D) 133 #define PPSMC_HasDisplay ((uint16_t)0x5E) 134 #define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60) 135 #define PPSMC_MSG_UVDPowerON ((uint16_t)0x61) 136 #define PPSMC_MSG_EnableULV ((uint16_t)0x62) 137 #define PPSMC_MSG_DisableULV ((uint16_t)0x63) 138 #define PPSMC_MSG_EnterULV ((uint16_t)0x64) 139 #define PPSMC_MSG_ExitULV ((uint16_t)0x65) 140 #define PPSMC_PowerShiftActive ((uint16_t)0x6A) 141 #define PPSMC_PowerShiftInactive ((uint16_t)0x6B) 142 #define PPSMC_OCPActive ((uint16_t)0x6C) 143 #define PPSMC_OCPInactive ((uint16_t)0x6D) 144 #define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E) 145 #define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F) 146 #define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70) 147 #define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71) 148 #define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72) 149 #define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73) 150 #define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74) 151 #define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75) 152 #define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76) 153 #define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77) 154 #define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78) 155 #define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79) 156 #define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A) 157 #define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B) 158 #define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C) 159 #define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D) 160 161 #define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E) 162 #define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F) 163 #define PPSMC_FlushDataCache ((uint16_t)0x80) 164 #define PPSMC_FlushInstrCache ((uint16_t)0x81) 165 166 #define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82) 167 #define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83) 168 169 #define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84) 170 171 #define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85) 172 #define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86) 173 #define PPSMC_MSG_EnableDTE ((uint16_t)0x87) 174 #define PPSMC_MSG_DisableDTE ((uint16_t)0x88) 175 176 #define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89) 177 178 #define PPSMC_MSG_BREAK ((uint16_t)0xF8) 179 180 /* Trinity Specific Messages*/ 181 #define PPSMC_MSG_Test ((uint16_t) 0x100) 182 #define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101) 183 #define PPSMC_MSG_DPM_Config ((uint16_t) 0x102) 184 #define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103) 185 #define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104) 186 #define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105) 187 #define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106) 188 #define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107) 189 #define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108) 190 #define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109) 191 #define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a) 192 #define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b) 193 #define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e) 194 #define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f) 195 #define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110) 196 #define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111) 197 #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112) 198 #define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113) 199 #define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114) 200 #define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117) 201 #define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118) 202 #define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119) 203 #define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a) 204 #define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b) 205 #define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c) 206 #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d) 207 #define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e) 208 #define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f) 209 #define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120) 210 #define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121) 211 #define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122) 212 #define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123) 213 #define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124) 214 #define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125) 215 #define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126) 216 #define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127) 217 #define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128) 218 219 #define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129) 220 #define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A) 221 #define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B) 222 #define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C) 223 #define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) 224 #define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) 225 #define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) 226 #define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) 227 #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) 228 #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) 229 #define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) 230 #define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134) 231 #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) 232 #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) 233 #define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) 234 #define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) 235 #define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) 236 #define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) 237 #define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b) 238 #define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c) 239 #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) 240 #define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e) 241 #define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f) 242 #define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) 243 #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) 244 #define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142) 245 #define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143) 246 #define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144) 247 #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) 248 #define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) 249 #define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) 250 #define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) 251 #define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149) 252 #define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) 253 #define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b) 254 255 #define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c) 256 #define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d) 257 258 #define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e) 259 #define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f) 260 #define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150) 261 #define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151) 262 #define PPSMC_MSG_LCLKDPM_Enable ((uint16_t) 0x152) 263 #define PPSMC_MSG_LCLKDPM_Disable ((uint16_t) 0x153) 264 #define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154) 265 #define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155) 266 #define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156) 267 #define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157) 268 #define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158) 269 #define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159) 270 #define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a) 271 #define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b) 272 #define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t) 0x15c) 273 #define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d) 274 #define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e) 275 #define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) 276 #define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160) 277 #define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161) 278 #define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) 279 #define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163) 280 #define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164) 281 #define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165) 282 #define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166) 283 #define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) 284 #define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168) 285 #define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) 286 #define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) 287 #define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b) 288 #define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t) 0x16c) 289 #define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t) 0x16d) 290 #define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t) 0x16e) 291 #define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t) 0x16f) 292 #define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170) 293 #define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171) 294 #define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172) 295 #define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173) 296 #define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174) 297 #define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175) 298 #define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176) 299 #define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177) 300 #define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178) 301 #define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179) 302 #define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a) 303 #define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b) 304 #define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c) 305 #define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d) 306 #define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e) 307 #define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f) 308 #define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180) 309 #define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181) 310 #define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182) 311 #define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184) 312 #define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) 313 #define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) 314 #define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) 315 #define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) 316 #define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) 317 #define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) 318 #define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) 319 #define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) 320 #define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D) 321 #define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E) 322 #define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) 323 #define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) 324 #define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) 325 #define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192) 326 #define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193) 327 #define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194) 328 #define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195) 329 #define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207) 330 #define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196) 331 #define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208) 332 #define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197) 333 #define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198) 334 #define PPSMC_MSG_SetTjMax ((uint16_t) 0x199) 335 #define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) 336 #define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B) 337 #define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) 338 #define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) 339 340 #define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) 341 #define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) 342 #define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202) 343 #define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203) 344 #define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204) 345 #define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205) 346 #define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206) 347 #define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209) 348 #define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A) 349 350 #define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240) 351 #define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241) 352 #define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242) 353 #define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243) 354 #define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244) 355 #define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245) 356 #define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246) 357 358 #define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250) 359 #define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251) 360 #define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252) 361 #define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253) 362 #define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254) 363 #define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255) 364 #define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256) 365 #define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257) 366 #define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258) 367 #define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259) 368 #define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A) 369 #define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B) 370 #define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C) 371 #define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D) 372 #define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260) 373 #define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261) 374 #define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262) 375 #define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263) 376 #define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264) 377 #define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265) 378 #define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266) 379 #define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267) 380 #define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268) 381 #define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269) 382 #define PPSMC_MSG_EnableAvfs ((uint16_t) 0x26A) 383 #define PPSMC_MSG_DisableAvfs ((uint16_t) 0x26B) 384 #define PPSMC_MSG_PerformBtc ((uint16_t) 0x26C) 385 #define PPSMC_MSG_GetHbmCode ((uint16_t) 0x26D) 386 #define PPSMC_MSG_GetVrVddcTemperature ((uint16_t) 0x26E) 387 #define PPSMC_MSG_GetVrMvddTemperature ((uint16_t) 0x26F) 388 #define PPSMC_MSG_GetLiquidTemperature ((uint16_t) 0x270) 389 #define PPSMC_MSG_GetPlxTemperature ((uint16_t) 0x271) 390 #define PPSMC_MSG_RequestI2CControl ((uint16_t) 0x272) 391 #define PPSMC_MSG_ReleaseI2CControl ((uint16_t) 0x273) 392 #define PPSMC_MSG_LedConfig ((uint16_t) 0x274) 393 #define PPSMC_MSG_SetHbmFanCode ((uint16_t) 0x275) 394 #define PPSMC_MSG_SetHbmThrottleCode ((uint16_t) 0x276) 395 396 #define PPSMC_MSG_GetEnabledPsm ((uint16_t) 0x400) 397 #define PPSMC_MSG_AgmStartPsm ((uint16_t) 0x401) 398 #define PPSMC_MSG_AgmReadPsm ((uint16_t) 0x402) 399 #define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403) 400 #define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404) 401 402 /* AVFS Only - Remove Later */ 403 #define PPSMC_MSG_VftTableIsValid ((uint16_t) 0x666) 404 405 /* If the SMC firmware has an event status soft register this is what the individual bits mean.*/ 406 #define PPSMC_EVENT_STATUS_THERMAL 0x00000001 407 #define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002 408 #define PPSMC_EVENT_STATUS_DC 0x00000004 409 410 typedef uint16_t PPSMC_Msg; 411 412 #pragma pack(pop) 413 414 #endif 415
Indexes created Tue Sep 30 17:09:57 GMT 2025