| /src/sys/dev/ic/ |
| igpioreg.h | 132 { "INT3455", 0, 0, 58, 0x100, 0x110 },
133 { "INT3455", 1, 59, 152, 0x100, 0x110 },
134 { "INT3455", 2, 153, 215, 0x100, 0x110 },
135 { "INT3455", 3, 216, 240, 0x100, 0x110 },
144 { "INT34C4", 0, 0, 59, 0x100, 0x110 },
145 { "INT34C4", 1, 60, 148, 0x100, 0x110 },
146 { "INT34C4", 2, 149, 237, 0x100, 0x110 },
147 { "INT34C4", 3, 238, 266, 0x100, 0x110 },
195 { "INT3536", 0, 0, 71, 0x100, 0x110 },
196 { "INT3536", 1, 72, 132, 0x100, 0x110 },
[all...] |
| /src/sys/arch/arm/imx/ |
| imx23_apbxdmareg.h | 50 #define HW_APBX_CH0_NXTCMDAR 0x110
|
| imx23_apbhdmareg.h | 220 #define HW_APBH_CH1_DEBUG2 0x110
|
| imx23_mmcreg.h | 236 #define HW_SSP_VERSION 0x110
|
| /src/sys/arch/arm/nvidia/ |
| tegra_pciereg.h | 59 #define AFI_PEXn_CTRL_REG(n) (0x110 + (n) * 8)
|
| tegra124_xusbpadreg.h | 100 #define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL4_REG 0x110
|
| /src/sys/arch/arm/samsung/ |
| mct_reg.h | 38 #define MCT_G_CNT_WSTAT 0x110 /* wait for write OK cntr */
|
| /src/sys/arch/hpcmips/dev/ |
| plumicureg.h | 74 #define PLUM_INT_EXTIEN_REG 0x110
|
| /src/sys/arch/ia64/include/ |
| setjmp.h | 64 #define J_F23 0x110
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/ |
| lpc18xx-ccu.h | 17 #define CLK_APB3_DAC 0x110
|
| am3.h | 45 #define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110)
|
| omap5.h | 81 #define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110)
|
| /src/sys/arch/powerpc/include/ |
| spr.h | 136 #define SPR_SPRG0 0x110 /* E468 SPR General 0 */
|
| /src/sys/dev/pci/qat/ |
| qat_c3xxxreg.h | 115 #define RICPPINTCTL_C3XXX (0x3A000 + 0x110)
|
| qat_c62xreg.h | 118 #define RICPPINTCTL_C62X (0x3A000 + 0x110)
|
| qat_d15xxreg.h | 118 #define RICPPINTCTL_D15XX (0x3A000 + 0x110)
|
| /src/sys/arch/amiga/dev/ |
| ioblix_zbus.c | 93 { "com", 0x110, 24000000 },
|
| /src/sys/arch/arm/broadcom/ |
| bcm2835_cm.h | 147 #define CM_PLLH 0x110
|
| /src/sys/arch/arm/ixp12x0/ |
| ixp12x0_pcireg.h | 106 #define DRAM_ADDR_SIZE_0 0x110
|
| /src/sys/arch/arm/marvell/ |
| mvsocreg.h | 122 #define MVSOC_MLMB_MLMBICR 0x110 /*Mb-L to Mb Bridge Intr Cause*/
|
| /src/sys/arch/sh3/include/ |
| pcicreg.h | 69 #define SH4_PCILAR1 (SH4_PCIC+0x110) /* 32bit */
|
| /src/sys/dev/pci/ |
| if_nfereg.h | 63 #define NFE_LINKSPEED 0x110
|
| /src/sys/dev/tc/ |
| ioasicreg.h | 106 #define IOASIC_INTR IOASIC_SLOT_1_START+0x110
|
| /src/sys/dev/usb/ |
| if_smscreg.h | 143 #define SMSC_HASHL 0x110
|
| /src/sys/arch/hpcmips/tx/ |
| tx39icureg.h | 48 #define TX39_INTRSTATUS5_REG 0x110
68 #define TX39_INTRCLEAR5_REG 0x110
|
