1/* $NetBSD: imx23_mmcreg.h,v 1.2 2026/02/02 06:23:37 skrll Exp $ */
2
3/*
4 * Copyright (c) 2012 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Petri Laakso.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _ARM_IMX_IMX23_SSPREG_H_
33#define _ARM_IMX_IMX23_SSSREG_H_
34
35#include <sys/cdefs.h>
36
37#define HW_SSP1_BASE 0x80010000
38#define HW_SSP1_SIZE 0x2000
39
40#define HW_SSP2_BASE 0x80034000
41#define HW_SSP2_SIZE 0x2000
42
43/*
44 * SSP Control Register 0.
45 */
46#define HW_SSP_CTRL0		0x000
47#define HW_SSP_CTRL0_SET	0x004
48#define HW_SSP_CTRL0_CLR	0x008
49#define HW_SSP_CTRL0_TOG	0x00C
50
51#define HW_SSP_CTRL0_SFTRST		__BIT(31)
52#define HW_SSP_CTRL0_CLKGATE		__BIT(30)
53#define HW_SSP_CTRL0_RUN		__BIT(29)
54#define HW_SSP_CTRL0_SDIO_IRQ_CHECK	__BIT(28)
55#define HW_SSP_CTRL0_LOCK_CS		__BIT(27)
56#define HW_SSP_CTRL0_IGNORE_CRC		__BIT(26)
57#define HW_SSP_CTRL0_READ		__BIT(25)
58#define HW_SSP_CTRL0_DATA_XFER		__BIT(24)
59#define HW_SSP_CTRL0_BUS_WIDTH		__BITS(23, 22)
60#define HW_SSP_CTRL0_WAIT_FOR_IRQ	__BIT(21)
61#define HW_SSP_CTRL0_WAIT_FOR_CMD	__BIT(20)
62#define HW_SSP_CTRL0_LONG_RESP		__BIT(19)
63#define HW_SSP_CTRL0_CHECK_RESP		__BIT(18)
64#define HW_SSP_CTRL0_GET_RESP		__BIT(17)
65#define HW_SSP_CTRL0_ENABLE		__BIT(16)
66#define HW_SSP_CTRL0_XFER_COUNT		__BITS(15, 0)
67
68/*
69 * SD/MMC Command Register 0.
70 */
71#define HW_SSP_CMD0	0x010
72#define HW_SSP_CMD0_SET	0x014
73#define HW_SSP_CMD0_CLR	0x018
74#define HW_SSP_CMD0_TOG	0x01C
75
76#define HW_SSP_CMD0_RSVD0		__BITS(31, 23)
77#define HW_SSP_CMD0_SLOW_CLKING_EN	__BIT(22)
78#define HW_SSP_CMD0_CONT_CLKING_EN	__BIT(21)
79#define HW_SSP_CMD0_APPEND_8CYC		__BIT(20)
80#define HW_SSP_CMD0_BLOCK_SIZE		__BITS(19, 16)
81#define HW_SSP_CMD0_BLOCK_COUNT		__BITS(15, 8)
82#define HW_SSP_CMD0_CMD			__BITS(7, 0)
83
84/*
85 * SD/MMC Command Register 1.
86 */
87#define HW_SSP_CMD1	0x020
88
89#define HW_SSP_CMD1_CMD_ARG	__BITS(31, 0)
90
91/*
92 * SD/MMC Compare Reference.
93 */
94#define HW_SSP_COMPREF	0x030
95
96#define HW_SSP_COMPREF_REFERENCE	__BITS(31, 0)
97
98/*
99 * SD/MMC compare mask.
100 */
101#define HW_SSP_COMPMASK	0x040
102
103#define HW_SSP_COMPMASK_MASK	__BITS(31, 0)
104
105/*
106 * SSP Timing Register.
107 */
108#define HW_SSP_TIMING	0x050
109
110#define HW_SSP_TIMING_TIMEOUT		__BITS(31, 16)
111#define HW_SSP_TIMING_CLOCK_DIVIDE	__BITS(15, 8)
112#define HW_SSP_TIMING_CLOCK_RATE	__BITS(7, 0)
113
114/*
115 * SSP Control Register 1.
116 */
117#define HW_SSP_CTRL1		0x060
118#define HW_SSP_CTRL1_SET	0x064
119#define HW_SSP_CTRL1_CLR	0x068
120#define HW_SSP_CTRL1_TOG	0x06C
121
122#define HW_SSP_CTRL1_SDIO_IRQ			__BIT(31)
123#define HW_SSP_CTRL1_SDIO_IRQ_EN		__BIT(30)
124#define HW_SSP_CTRL1_RESP_ERR_IRQ		__BIT(29)
125#define HW_SSP_CTRL1_RESP_ERR_IRQ_EN		__BIT(28)
126#define HW_SSP_CTRL1_RESP_TIMEOUT_IRQ		__BIT(27)
127#define HW_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN	__BIT(26)
128#define HW_SSP_CTRL1_DATA_TIMEOUT_IRQ		__BIT(25)
129#define HW_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN	__BIT(24)
130#define HW_SSP_CTRL1_DATA_CRC_IRQ		__BIT(23)
131#define HW_SSP_CTRL1_DATA_CRC_IRQ_EN		__BIT(22)
132#define HW_SSP_CTRL1_FIFO_UNDERRUN_IRQ		__BIT(21)
133#define HW_SSP_CTRL1_FIFO_UNDERRUN_EN		__BIT(20)
134#define HW_SSP_CTRL1_RSVD3			__BIT(19)
135#define HW_SSP_CTRL1_RSVD2			__BIT(18)
136#define HW_SSP_CTRL1_RECV_TIMEOUT_IRQ		__BIT(17)
137#define HW_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN	__BIT(16)
138#define HW_SSP_CTRL1_FIFO_OVERRUN_IRQ		__BIT(15)
139#define HW_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN	__BIT(14)
140#define HW_SSP_CTRL1_DMA_ENABLE			__BIT(13)
141#define HW_SSP_CTRL1_RSVD1			__BIT(12)
142#define HW_SSP_CTRL1_SLAVE_OUT_DISABLE		__BIT(11)
143#define HW_SSP_CTRL1_PHASE			__BIT(10)
144#define HW_SSP_CTRL1_POLARITY			__BIT(9)
145#define HW_SSP_CTRL1_SLAVE_MODE			__BIT(8)
146#define HW_SSP_CTRL1_WORD_LENGTH		__BITS(7, 4)
147#define HW_SSP_CTRL1_SSP_MODE			__BITS(3, 0)
148
149/*
150 * SSP Data Register.
151 */
152#define HW_SSP_DATA	0x070
153
154#define HW_SSP_DATA_DATA	__BITS(31, 0)
155
156/*
157 * SD/MMC Card Response Register 0.
158 */
159#define HW_SSP_SDRESP0	0x080
160
161#define HW_SSP_SDRESP0_RESP0	__BITS(31, 0)
162
163/*
164 * SD/MMC Card Response Register 1.
165 */
166#define HW_SSP_SDRESP1	0x090
167
168#define HW_SSP_SDRESP1_RESP1	__BITS(31, 0)
169
170/*
171 * SD/MMC Card Response Register 2.
172 */
173#define HW_SSP_SDRESP2	0x0A0
174
175#define HW_SSP_SDRESP2_RESP2	__BITS(31, 0)
176
177/*
178 * SD/MMC Card Response Register 3.
179 */
180#define HW_SSP_SDRESP3	0x0B0
181
182#define HW_SSP_SDRESP3_RESP3	__BITS(31, 0)
183
184/*
185 * SSP Status Register.
186 */
187#define HW_SSP_STATUS	0x0C0
188
189#define HW_SSP_STATUS_PRESENT		__BIT(31)
190#define HW_SSP_STATUS_RSVD5		__BIT(30)
191#define HW_SSP_STATUS_SD_PRESENT	__BIT(29)
192#define HW_SSP_STATUS_CARD_DETECT	__BIT(28)
193#define HW_SSP_STATUS_RSVD4		__BITS(27, 22)
194#define HW_SSP_STATUS_DMASENSE		__BIT(21)
195#define HW_SSP_STATUS_DMATERM		__BIT(20)
196#define HW_SSP_STATUS_DMAREQ		__BIT(19)
197#define HW_SSP_STATUS_DMAEND		__BIT(18)
198#define HW_SSP_STATUS_SDIO_IRQ		__BIT(17)
199#define HW_SSP_STATUS_RESP_CRC_ERR	__BIT(16)
200#define HW_SSP_STATUS_RESP_ERR		__BIT(15)
201#define HW_SSP_STATUS_RESP_TIMEOUT	__BIT(14)
202#define HW_SSP_STATUS_DATA_CRC_ERR	__BIT(13)
203#define HW_SSP_STATUS_TIMEOUT		__BIT(12)
204#define HW_SSP_STATUS_RECV_TIMEOUT_STAT	__BIT(11)
205#define HW_SSP_STATUS_RSVD3		__BIT(10)
206#define HW_SSP_STATUS_FIFO_OVRFLW	__BIT(9)
207#define HW_SSP_STATUS_FIFO_FULL		__BIT(8)
208#define HW_SSP_STATUS_RSVD2		__BIT(7, 6)
209#define HW_SSP_STATUS_FIFO_EMPTY	__BIT(5)
210#define HW_SSP_STATUS_FIFO_UNDRFLW	__BIT(4)
211#define HW_SSP_STATUS_CMD_BUSY		__BIT(3)
212#define HW_SSP_STATUS_DATA_BUSY		__BIT(2)
213#define HW_SSP_STATUS_RSVD1		__BIT(1)
214#define HW_SSP_STATUS_BUSY		__BIT(0)
215
216/*
217 * SSP Debug Register.
218 */
219#define HW_SSP_DEBUG	0x100
220
221#define HW_SSP_DEBUG_DATACRC_ERR	__BITS(31, 28)
222#define HW_SSP_DEBUG_DATA_STALL		__BIT(27)
223#define HW_SSP_DEBUG_DAT_SM		__BITS(26, 24)
224#define HW_SSP_DEBUG_RSVD1		__BITS(23, 20)
225#define HW_SSP_DEBUG_CMD_OE		__BIT(19)
226#define HW_SSP_DEBUG_DMA_SM		__BITS(18, 16)
227#define HW_SSP_DEBUG_MMC_SM		__BITS(15, 12)
228#define HW_SSP_DEBUG_CMD_SM		__BITS(11, 10)
229#define HW_SSP_DEBUG_SSP_CMD		__BIT(9)
230#define HW_SSP_DEBUG_SSP_RESP		__BIT(8)
231#define HW_SSP_DEBUG_SSP_RXD		__BITS(7, 0)
232
233/*
234 * SSP Version Register.
235 */
236#define HW_SSP_VERSION	0x110
237
238#define HW_SSP_VERSION_MAJOR	__BITS(31, 24)
239#define HW_SSP_VERSION_MINOR	__BITS(23, 16)
240#define HW_SSP_VERSION_STEP	__BITS(15, 0)
241
242#endif /* !_ARM_IMX_IMX23_SSPREG_H_ */
243