| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/vp/ |
| nouveau_nvkm_engine_vp_g84.c | 35 .fifo_val = 0x111,
|
| /src/sys/arch/powerpc/include/ |
| spr.h | 137 #define SPR_SPRG1 0x111 /* E468 SPR General 1 */
|
| /src/tests/lib/libcurses/tests/ |
| std_defines | 54 assign KEY_F9 0x111
|
| /src/sys/arch/hpcmips/dev/ |
| ite8181reg.h | 92 #define ITE8181_GUI_CC0R1 0x111
|
| /src/lib/libform/ |
| form.h | 101 #define REQ_NEXT_CHAR (KEY_MAX + 0x111) /* move to the next char
|
| /src/sys/arch/powerpc/include/ibm4xx/ |
| dcr4xx.h | 113 #define DCR_DMA0_CT2 0x111 /* DMA Count Register 2 */
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
| imx8mm-beacon-som.dtsi | 459 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
|
| imx8mn-beacon-som.dtsi | 470 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| fiji_ppsmc.h | 196 #define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111)
|
| smu7_ppsmc.h | 193 #define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111)
|
| tonga_ppsmc.h | 217 #define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111)
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_overlay.c | 422 nvif_wr32(dev, NV_PVIDEO_CONTROL_X, 0x111); /* (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/ |
| linux-event-codes.h | 358 #define BTN_RIGHT 0x111
|
| /src/sys/arch/powerpc/powerpc/ |
| db_disasm.c | 437 { 0x111, "sprg1" },
569 { 0x111, "dma0_ct2" },
|
| /src/sys/arch/amiga/dev/ |
| grfabs_ccglb.c | 638 0x000, 0x111, 0x222, 0x333,
|
| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_dp_helper.h | 504 #define DP_MSTM_CTRL 0x111 /* 1.2 */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/ |
| bif_5_0_d.h | 419 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x111
|
| /src/sys/dev/isa/ |
| aria.c | 338 aria_do_kludge(iot, ioh, ioh1, 0x111,
|
| /src/sys/dev/qbus/ |
| qfont.c | 96 ,0x10e ,0x10f ,0x110 ,0x111 ,0x00 ,0x00 ,0x00 ,0x00 /* 128 */
131 ,0x10e ,0x10f ,0x110 ,0x111 ,0x00 ,0x00 ,0x00 ,0x00 /* 128 */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| gfx_8_0_enum.h | 401 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1= 0x111,
1601 SC_PKR_CONTROL_XFER = 0x111,
2558 SQ_PERF_SEL_INSTS_SMEM_NORM = 0x111,
3563 #define SQ_DPP_ROW_SR1 0x111
|
| gfx_8_1_enum.h | 401 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1= 0x111,
1619 SC_PKR_CONTROL_XFER = 0x111,
2576 SQ_PERF_SEL_INSTS_SMEM_NORM = 0x111,
3581 #define SQ_DPP_ROW_SR1 0x111
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/ |
| gmc_7_1_d.h | 1174 #define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x111
|
| gmc_8_1_d.h | 1278 #define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x111
|
| /src/sys/arch/shark/shark/ |
| sequoia.h | 2928 ** SEQUOIA-1 Pin Select Register 2 (SEQPSR2) - Index 0x111
2948 #define SEQR_SEQPSR2_REG 0x111
|
| /src/sys/lib/libkern/arch/hppa/ |
| milli.S | 1305 x111: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1 label
|
