| /src/sys/dev/ic/ |
| igpioreg.h | 98 { "INT344B", 0, 0, 47, 0x100, 0x120 },
99 { "INT344B", 1, 48, 119, 0x100, 0x120 },
100 { "INT344B", 2, 120, 151, 0x100, 0x120 },
103 { "INT3451", 0, 0, 47, 0x100, 0x120 },
104 { "INT3451", 1, 48, 180, 0x100, 0x120 },
105 { "INT3451", 2, 181, 191, 0x100, 0x120 },
108 { "INT345D", 0, 0, 47, 0x100, 0x120 },
109 { "INT345D", 1, 48, 180, 0x100, 0x120 },
110 { "INT345D", 2, 181, 191, 0x100, 0x120 },
121 { "INT3450", 0, 0, 50, 0x100, 0x120 },
[all...] |
| /src/sys/arch/evbmips/malta/dev/ |
| gtreg.h | 8 #define GT_MULTIGT 0x120
|
| /src/sys/arch/sun3/dev/ |
| sereg.h | 100 char se_pad[0x10000 - 0x120];
|
| /src/sys/arch/ia64/include/ |
| setjmp.h | 65 #define J_F24 0x120
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/ |
| lpc18xx-ccu.h | 19 #define CLK_APB3_ADC1 0x120
|
| am3.h | 72 #define AM3_L4HS_CLKCTRL_OFFSET 0x120
74 #define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120)
|
| am4.h | 14 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
16 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
|
| omap4.h | 120 #define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120)
|
| omap5.h | 83 #define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120)
|
| /src/sys/arch/alpha/pci/ |
| lcareg.h | 113 #define LCA_IOC_W_BASE1 (LCA_IOC_BASE + 0x120) /* Window Base */
|
| /src/sys/arch/arc/jazz/ |
| rd94.h | 63 #define RD94_SYS_DMA1_REGS (RD94SYS+0x120) /* DMA ch0 base address */
|
| /src/sys/arch/sh3/include/ |
| exception.h | 62 #define EXPEVT_FPU 0x120 /* FPU exception */
|
| pcicreg.h | 73 #define SH4_PCICLR (SH4_PCIC+0x120) /* 32bit */
|
| /src/sys/dev/pcmcia/ |
| if_cnwreg.h | 69 #define CNW_EREG_RSER 0x120
|
| /src/sys/arch/arm/broadcom/ |
| bcm2835_cm.h | 151 #define CM_DSIOHSCK 0x120
|
| /src/sys/arch/arm/ixp12x0/ |
| ixp12x0_pcireg.h | 110 #define I2O_IFH 0x120
|
| /src/sys/arch/arm/nvidia/ |
| tegra124_xusbpadreg.h | 104 #define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL5_REG 0x120
|
| /src/sys/dev/isa/ |
| adv_isa.c | 83 0x120,
|
| /src/sys/dev/tc/ |
| ioasicreg.h | 107 #define IOASIC_IMSK IOASIC_SLOT_1_START+0x120
|
| /src/sys/dev/usb/ |
| if_smscreg.h | 147 #define SMSC_VLAN1 0x120
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/ |
| stingray-pinctrl.dtsi | 178 0x120 MODE_NITRO /* dbu_txd */
185 0x120 MODE_NAND /* uart1_out */
|
| /src/sys/arch/amiga/amiga/ |
| cc_registers.h | 170 #define R_SPR0PTH 0x120
|
| /src/sys/arch/arm/footbridge/ |
| dc21285reg.h | 186 #define I2O_INBOUND_FREE_HEAD 0x120
|
| /src/sys/arch/arm/imx/ |
| imx23_clkctrlreg.h | 294 #define HW_CLKCTRL_RESET 0x120
|
| imx23_icollreg.h | 240 #define HW_ICOLL_INTERRUPT0 0x120
|
