/src/tests/kernel/arch/aarch64/ |
execsp.S | 44 adrp x17, _C_LABEL(startsp) 45 str x16, [x17, :lo12:_C_LABEL(startsp)] 57 adrp x17, _C_LABEL(ctorsp) 58 str x16, [x17, :lo12:_C_LABEL(ctorsp)] 76 adrp x17, _C_LABEL(mainsp) 77 str x16, [x17, :lo12:_C_LABEL(mainsp)] 91 adrp x17, _C_LABEL(dtorsp) 92 str x16, [x17, :lo12:_C_LABEL(dtorsp)]
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execregs.c | 71 register long x17 __asm("x17") = nonnull(17); 109 "+r"(x17) 149 register long x17 __asm("x17") = nonnull(17); 198 "+r"(x17),
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/src/sys/arch/hp300/stand/common/ |
kbdmap.h | 50 #define KBD_UK 0x17 /* United Kingdom */
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grf_hyreg.h | 68 vu_char bits; /* square(0)/double-high(1) 0x17 */ 69 u_char f1[0x5b-0x17-1];
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/src/sys/arch/sgimips/dev/ |
int2reg.h | 46 #define INT2_MAP_MASK0 0x17
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/src/sys/external/gpl2/dts/dist/include/dt-bindings/soc/ |
qcom,apr.h | 28 #define APR_SVC_MAX 0x17
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/src/sys/netinet/ |
igmp.h | 103 #define IGMP_HOST_LEAVE_MESSAGE 0x17 /* leave-group message */
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/src/lib/libc/arch/aarch64/sys/ |
__syscall.S | 52 * First we move the syscall number to x17 freeing a register. 59 mov x17, x0
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/src/sys/external/gpl2/dts/dist/include/dt-bindings/dma/ |
x1000-dma.h | 28 #define X1000_DMA_SSI0_RX 0x17
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x1830-dma.h | 26 #define X1830_DMA_SSI0_RX 0x17
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jz4775-dma.h | 30 #define JZ4775_DMA_SSI0_RX 0x17
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x2000-dma.h | 31 #define X2000_DMA_SSI0_RX 0x17
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/src/sys/arch/x68k/dev/ |
rtclock_var.h | 71 #define RTC_YEAR 0x17 89 #define RTC_LEAP 0x17
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/src/libexec/ld.elf_so/arch/aarch64/ |
rtld_start.S | 92 mov x17, x0 /* save entry point */ 97 br x17 /* call saved entry point */ 129 mov x17, x0 /* save result */ 145 br x17 /* call bound function */ 279 stp x17, x18, [sp, #(7 * 16)] 292 .cfi_rel_offset x17, 112 306 ldp x17, x18, [sp, #(7 * 16)]
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/src/sys/arch/mips/include/ |
cache_r5k.h | 65 #define CACHEOP_R5K_Page_Invalidate_S 0x17
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/src/sys/dev/i2c/ |
am2315reg.h | 50 #define AM2315_REGISTER_RETENTION_17 0x17
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/src/sys/dev/sun/ |
idprom.h | 74 #define ID_SUN3_60 0x17 /* Sun3F */
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/src/sys/dev/usb/ |
emdtvreg.h | 75 #define EM28XX_IR_VOLUME_DOWN 0x17
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kue_fw.h | 134 0xe7, 0x09, 0x94, 0x08, 0xae, 0x08, 0xe7, 0x17, 145 0xc0, 0x57, 0xb4, 0x05, 0x1b, 0xc8, 0xc0, 0x17, 148 0x00, 0x02, 0xc0, 0x17, 0x4c, 0x00, 0x30, 0x00, 161 0xc0, 0x17, 0x0e, 0x00, 0x27, 0x00, 0x34, 0x01, 176 0x27, 0x50, 0x34, 0x01, 0x17, 0xc1, 0xe7, 0x77, 193 0xac, 0x08, 0xf2, 0x17, 0x01, 0x00, 0x5c, 0x00, 211 0x97, 0xcf, 0x27, 0x04, 0x72, 0x08, 0xc8, 0x17, 228 0x00, 0x02, 0xc0, 0x17, 0x0c, 0x00, 0x30, 0x00, 230 0xc8, 0x17, 0x04, 0x00, 0xc1, 0x07, 0x02, 0x00, 235 0x6c, 0x08, 0xc0, 0xdf, 0x17, 0x02, 0xc8, 0x17 [all...] |
/src/sys/arch/mac68k/include/ |
keyboard.h | 58 #define ADBK_5 0x17 92 { /* 0x0D, */ 'w', 'W', 0x17 }, 102 { /* 0x17, */ '5', '%', 0x00 },
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/src/sys/arch/macppc/include/ |
keyboard.h | 58 #define ADBK_5 0x17 96 { /* 0x0D, */ 'w', 'W', 0x17, 17 }, 106 { /* 0x17, */ '5', '%', 0x00, 6 },
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/src/sys/dev/ic/ |
ninjaata32reg.h | 92 #define NJATA32_REG_WD_COMMAND 0x17 /* len=1 WO */ 93 #define NJATA32_REG_WD_STATUS 0x17 /* len=1 RO */
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/src/sbin/scsictl/ |
scsi_sense.c | 142 { 0x17, 0x00, "Recovered Data With No Error Correction Applied" }, 143 { 0x17, 0x01, "Recovered Data With Retries" }, 144 { 0x17, 0x02, "Recovered Data With Positive Head Offset" }, 145 { 0x17, 0x03, "Recovered Data With Negative Head Offset" }, 146 { 0x17, 0x04, "Recovered Data With Retries and/or CIRC Applied" }, 147 { 0x17, 0x05, "Recovered Data Using Previous Sector ID" }, 148 { 0x17, 0x06, "Recovered Data Without ECC - Data Auto-Reallocated" }, 149 { 0x17, 0x07, "Recovered Data Without ECC - Recommend Reassignment" }, 150 { 0x17, 0x08, "Recovered Data Without ECC - Recommend Rewrite" },
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/src/sys/external/bsd/drm2/dist/drm/amd/include/ivsrcid/dcn/ |
irqsrcs_dcn_1_0.h | 530 #define DCN_1_0__SRCID__OTG1_CPU_SS_INT 0x17 // D1: OTG Static Screen interrupt OTG1_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 533 #define DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE 0x17 // D1 : OTG range timing OTG1_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 536 #define DCN_1_0__SRCID__OTG2_CPU_SS_INT 0x17 // D2 : OTG Static Screen interrupt OTG2_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 539 #define DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE 0x17 // D2 : OTG range timing OTG2_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 542 #define DCN_1_0__SRCID__OTG3_CPU_SS_INT 0x17 // D3 : OTG Static Screen interrupt OTG3_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 545 #define DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE 0x17 // D3 : OTG range timing OTG3_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 548 #define DCN_1_0__SRCID__OTG4_CPU_SS_INT 0x17 // D4 : OTG Static Screen interrupt OTG4_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 551 #define DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE 0x17 // D4 : OTG range timing OTG4_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 554 #define DCN_1_0__SRCID__OTG5_CPU_SS_INT 0x17 // D5 : OTG Static Screen interrupt OTG5_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 557 #define DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE 0x17 // D5 : OTG range timing OTG5_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pul (…) [all...] |
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
rk3288-veyron-jerry.dts | 92 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 96 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 99 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 103 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 107 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 111 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 115 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 119 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>; 126 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 130 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x1 [all...] |