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  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
dm816.h 25 #define DM816_TIMER2_CLKCTRL DM816_CLKCTRL_INDEX(0x174)
  /src/sys/arch/hp300/dev/
mtreg.h 34 #define MT7974AID 0x174
  /src/sys/dev/gpib/
mtreg.h 35 #define MT7974AID 0x174
  /src/tests/lib/libcurses/tests/
std_defines 99 assign KEY_REFERENCE 0x174
  /src/sys/arch/amiga/amiga/
cc_registers.h 212 #define R_SPR6_DATAA 0x174
  /src/sys/arch/arm/footbridge/
dc21285reg.h 285 #define UART_CONTROL 0x174
  /src/sys/arch/arm/ti/
omap2_gpmcreg.h 107 #define GPMC_NAND_DATA_5 0x174
  /src/sys/dev/ic/
mvsatareg.h 59 #define SATAHC_I_PHYMODE(p) ((p) * 0x100 + 0x174)
igsfbreg.h 364 #define IGS_COP_SRC2_START_REG 0x174
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 241 0x174 MODE_NITRO /* i2c1_sda */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
omap4-var-om44customboard.dtsi 98 OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */
vf610-pinfunc.h 590 #define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0
591 #define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0
592 #define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2
593 #define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1
594 #define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0
595 #define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0
596 #define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0
597 #define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0
imx6dl-pinfunc.h 456 #define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0
457 #define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1
458 #define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0
459 #define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1
460 #define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0
461 #define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0
462 #define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x174 0x544 0x900 0x4 0x0
463 #define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x174 0x544 0x000 0x4 0x0
464 #define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0
465 #define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x
    [all...]
imx25-pinfunc.h 403 #define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x00 0x000
404 #define MX25_PAD_UART1_TXD__UART2_DSR 0x174 0x36c 0x000 0x03 0x000
405 #define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x05 0x000
imx51-pinfunc.h 318 #define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0
319 #define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0
320 #define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0
321 #define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0
  /src/lib/libcurses/
keyname.c 327 if (key == 0x174) {
  /src/sys/arch/arm/imx/
imx23_digctlreg.h 294 #define HW_DIGCTL_OCRAM_STATUS6_SET 0x174
  /src/sys/arch/arm/nvidia/
tegra210_pinmux.c 154 TEGRA_PIN("pwr_int_n", 0x174, NULL, NULL, NULL, NULL),
tegra_hdmireg.h 241 #define HDMI_NV_PDISP_SOR_CRCB_REG 0x174
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mm-pinfunc.h 335 #define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
336 #define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
337 #define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
338 #define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
339 #define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
340 #define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
341 #define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
imx8mq-pinfunc.h 321 #define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
322 #define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
323 #define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
324 #define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
325 #define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
326 #define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
327 #define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
fiji_ppsmc.h 296 #define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174)
smu7_ppsmc.h 292 #define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174)
tonga_ppsmc.h 321 #define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174)
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/
linux-event-codes.h 444 #define KEY_FULL_SCREEN 0x174 /* AC View Toggle */

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