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  /src/sys/arch/rs6000/include/
iocc.h 55 #define IOCC_MIR (IOCC_BASE + 0x190) /* misc intr reg */
  /src/sys/arch/arm/nvidia/
tegra_pciereg.h 63 #define AFI_MSG_REG 0x190
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mm-evk.dts 82 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
93 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
imx8mm-icore-mx8mm-ctouch2.dts 70 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
imx8mm-icore-mx8mm-edimm2.2.dts 70 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
imx8mm-icore-mx8mm.dtsi 175 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
186 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
imx8mm-var-som.dtsi 432 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
471 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
507 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
517 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
imx8mn-var-som.dtsi 422 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
461 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
497 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
507 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
imx8mm-kontron-n801x-som.dtsi 243 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
254 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
imx8mm-venice-gw72xx.dtsi 262 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
273 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
imx8mm-venice-gw73xx.dtsi 313 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
324 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
imx8mp-phycore-som.dtsi 267 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
277 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
dm814.h 25 #define DM814_MCSPI1_CLKCTRL DM814_CLKCTRL_INDEX(0x190)
dm816.h 32 #define DM816_MCSPI1_CLKCTRL DM816_CLKCTRL_INDEX(0x190)
  /src/sys/arch/ia64/include/
setjmp.h 78 #define J_F31 0x190
  /src/sys/arch/arm/sunxi/
sunxi_can.h 138 #define SUNXI_CAN_RBUF_RBACK4 0x190
  /src/sys/dev/pcmcia/
if_cnwreg.h 103 #define CNW_EREG_STAT_RXMULTI 0x190
  /src/sys/arch/arm/ti/
omap2_gpmcreg.h 112 #define GPMC_CONFIG5_6 0x190
135 #define GPMC_CONFIG5_6 0x190
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
dra72x-mmc-iodelay.dtsi 300 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
325 0x190 A_DELAY_PS(695) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
350 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
  /src/sys/arch/arm/broadcom/
bcm2835_cm.h 130 #define CM_PULSECTL 0x190
  /src/sys/arch/arm/ixp12x0/
ixp12x0_pcireg.h 159 #define IXPPCI_IRQ_SOFT (IXP12X0_PCI_VBASE + 0x190)
  /src/sys/arch/hpcmips/tx/
tx39ioreg.h 42 #define TX39_IOMFIODATASEL_REG 0x190
  /src/sys/arch/sh3/include/
pcicreg.h 81 #define SH4_PCIDPA1 (SH4_PCIC+0x190) /* 32bit */
  /src/sys/dev/pci/
if_nfereg.h 74 #define NFE_PHY_CTL 0x190
  /src/sys/dev/tc/
ioasicreg.h 114 #define IOASIC_SCC1_DECODE IOASIC_SLOT_1_START+0x190

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