1 /* $NetBSD: ppsmc.h,v 1.3 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef PP_SMC_H 26 #define PP_SMC_H 27 28 #pragma pack(push, 1) 29 30 #define PPSMC_SWSTATE_FLAG_DC 0x01 31 #define PPSMC_SWSTATE_FLAG_UVD 0x02 32 #define PPSMC_SWSTATE_FLAG_VCE 0x04 33 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08 34 35 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 36 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 37 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff 38 39 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 40 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 41 #define PPSMC_SYSTEMFLAG_GDDR5 0x04 42 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 43 #define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 44 #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 45 #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO 0x40 46 47 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 48 #define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 49 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 50 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 51 #define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x02 52 53 #define PPSMC_DISPLAY_WATERMARK_LOW 0 54 #define PPSMC_DISPLAY_WATERMARK_HIGH 1 55 56 #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 57 #define PPSMC_STATEFLAG_POWERBOOST 0x02 58 #define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 59 #define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 60 61 #define FDO_MODE_HARDWARE 0 62 #define FDO_MODE_PIECE_WISE_LINEAR 1 63 64 enum FAN_CONTROL { 65 FAN_CONTROL_FUZZY, 66 FAN_CONTROL_TABLE 67 }; 68 69 #define PPSMC_Result_OK ((uint8_t)0x01) 70 #define PPSMC_Result_Failed ((uint8_t)0xFF) 71 72 typedef uint8_t PPSMC_Result; 73 74 #define PPSMC_MSG_Halt ((uint8_t)0x10) 75 #define PPSMC_MSG_Resume ((uint8_t)0x11) 76 #define PPSMC_MSG_ZeroLevelsDisabled ((uint8_t)0x13) 77 #define PPSMC_MSG_OneLevelsDisabled ((uint8_t)0x14) 78 #define PPSMC_MSG_TwoLevelsDisabled ((uint8_t)0x15) 79 #define PPSMC_MSG_EnableThermalInterrupt ((uint8_t)0x16) 80 #define PPSMC_MSG_RunningOnAC ((uint8_t)0x17) 81 #define PPSMC_MSG_SwitchToSwState ((uint8_t)0x20) 82 #define PPSMC_MSG_SwitchToInitialState ((uint8_t)0x40) 83 #define PPSMC_MSG_NoForcedLevel ((uint8_t)0x41) 84 #define PPSMC_MSG_ForceHigh ((uint8_t)0x42) 85 #define PPSMC_MSG_ForceMediumOrHigh ((uint8_t)0x43) 86 #define PPSMC_MSG_SwitchToMinimumPower ((uint8_t)0x51) 87 #define PPSMC_MSG_ResumeFromMinimumPower ((uint8_t)0x52) 88 #define PPSMC_MSG_EnableCac ((uint8_t)0x53) 89 #define PPSMC_MSG_DisableCac ((uint8_t)0x54) 90 #define PPSMC_TDPClampingActive ((uint8_t)0x59) 91 #define PPSMC_TDPClampingInactive ((uint8_t)0x5A) 92 #define PPSMC_StartFanControl ((uint8_t)0x5B) 93 #define PPSMC_StopFanControl ((uint8_t)0x5C) 94 #define PPSMC_MSG_NoDisplay ((uint8_t)0x5D) 95 #define PPSMC_NoDisplay ((uint8_t)0x5D) 96 #define PPSMC_MSG_HasDisplay ((uint8_t)0x5E) 97 #define PPSMC_HasDisplay ((uint8_t)0x5E) 98 #define PPSMC_MSG_UVDPowerOFF ((uint8_t)0x60) 99 #define PPSMC_MSG_UVDPowerON ((uint8_t)0x61) 100 #define PPSMC_MSG_EnableULV ((uint8_t)0x62) 101 #define PPSMC_MSG_DisableULV ((uint8_t)0x63) 102 #define PPSMC_MSG_EnterULV ((uint8_t)0x64) 103 #define PPSMC_MSG_ExitULV ((uint8_t)0x65) 104 #define PPSMC_CACLongTermAvgEnable ((uint8_t)0x6E) 105 #define PPSMC_CACLongTermAvgDisable ((uint8_t)0x6F) 106 #define PPSMC_MSG_CollectCAC_PowerCorreln ((uint8_t)0x7A) 107 #define PPSMC_FlushDataCache ((uint8_t)0x80) 108 #define PPSMC_MSG_SetEnabledLevels ((uint8_t)0x82) 109 #define PPSMC_MSG_SetForcedLevels ((uint8_t)0x83) 110 #define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84) 111 #define PPSMC_MSG_EnableDTE ((uint8_t)0x87) 112 #define PPSMC_MSG_DisableDTE ((uint8_t)0x88) 113 #define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint8_t)0x96) 114 #define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint8_t)0x97) 115 #define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149) 116 117 /* CI/KV/KB */ 118 #define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) 119 #define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) 120 #define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) 121 #define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) 122 #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) 123 #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) 124 #define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) 125 #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) 126 #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) 127 #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) 128 #define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) 129 #define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) 130 #define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) 131 #define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) 132 #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) 133 #define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) 134 #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) 135 #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) 136 #define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) 137 #define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) 138 #define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) 139 #define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) 140 #define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e) 141 #define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f) 142 #define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150) 143 #define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151) 144 #define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154) 145 #define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155) 146 #define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156) 147 #define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157) 148 #define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158) 149 #define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159) 150 #define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a) 151 #define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b) 152 #define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) 153 #define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) 154 #define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) 155 #define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) 156 #define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) 157 #define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) 158 #define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) 159 #define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) 160 #define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) 161 #define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) 162 #define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) 163 #define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) 164 #define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) 165 #define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) 166 #define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) 167 #define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) 168 #define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) 169 #define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205) 170 171 #define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) 172 #define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) 173 174 #define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) 175 #define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) 176 177 /* TN */ 178 #define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) 179 #define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104) 180 #define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108) 181 #define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109) 182 #define PPSMC_MSG_Thermal_Cntl_Enable ((uint32_t) 0x10a) 183 #define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e) 184 #define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f) 185 #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112) 186 #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d) 187 #define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e) 188 #define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120) 189 #define PPSMC_MSG_DisableBAPM ((uint32_t) 0x121) 190 #define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124) 191 192 #define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250) 193 #define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251) 194 #define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252) 195 #define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253) 196 #define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254) 197 198 typedef uint16_t PPSMC_Msg; 199 200 #pragma pack(pop) 201 202 #endif 203
Indexes created Sat Sep 20 22:09:52 GMT 2025