| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/ |
| nouveau_nvkm_engine_gr_ctxgk20a.c | 83 .attrib_nr_max = 0x240,
84 .attrib_nr = 0x240,
|
| /src/sys/arch/sh3/include/ |
| exception.h | 130 #define SH4_INTEVT_IRL0 0x240
137 #define SH4_INTEVT_IRQ2 0x240
|
| /src/games/bcd/ |
| bcd.c | 98 0x404, 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208,
102 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, 0x204,
114 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, 0x204,
118 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, 0x204,
|
| /src/sys/arch/arm/samsung/ |
| mct_reg.h | 45 #define MCT_G_TCON 0x240 /* configuration register */
|
| /src/sys/arch/x86/pci/ |
| lpssreg.h | 76 #define LPSS_REMAP_LO 0x240
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts | 19 qvga_timings: 320x240 {
|
| keystone-k2e.dtsi | 115 reg = <0x240 0x4>;
118 gpio,syscon-dev = <&devctrl 0x240>;
|
| ep7211-edb7211.dts | 33 timing0: 320x240 {
|
| omap2430.dtsi | 58 reg = <0x270 0x240>;
61 ranges = <0 0x270 0x240>;
|
| imx27-eukrea-mbimxsd27-baseboard.dts | 19 timing0: 320x240 {
|
| keystone-k2hk.dtsi | 93 reg = <0x240 0x4>;
96 gpio,syscon-dev = <&devctrl 0x240>;
|
| keystone-k2l.dtsi | 295 reg = <0x240 0x4>;
298 gpio,syscon-dev = <&devctrl 0x240>;
|
| imx25-pinfunc.h | 50 #define MX25_PAD_A19__A19 0x024 0x240 0x000 0x00 0x000
51 #define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x05 0x000
52 #define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x06 0x000
53 #define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x07 0x000
|
| /src/sys/arch/arm/clps711x/ |
| clps711xreg.h | 90 #define PS711X_INTSR 0x240 /* Interrupt Status Register (RO) */
|
| /src/sys/dev/isa/ |
| ioat66.c | 67 int ioatbases[NSLAVES]={0x220,0x228,0x240,0x248,0x260,0x268};
|
| if_ate.c | 81 0x260, 0x280, 0x2A0, 0x240, 0x340, 0x320, 0x380, 0x300
|
| if_fmv_isa.c | 79 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x300, 0x340
|
| essreg.h | 166 #define ESS_BASE_VALID(base) ((base) == 0x220 || (base) == 0x230 || (base) == 0x240 || (base) == 0x250)
|
| sbreg.h | 58 * either base I/O address 0x220 or 0x240. The encodings below give
291 #define SB_BASE_VALID(base) ((base) == 0x220 || (base) == 0x240 || (base) == 0x260)
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/ |
| am4.h | 54 #define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240)
164 #define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240)
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/ |
| stingray-pinctrl.dtsi | 334 0x240 MODE_NITRO /* drdu3_vbus_ppc */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_uvd_v4_2.c | 421 if (status & 0x240)
425 if (status & 0x240)
|
| amdgpu_vce_v2_0.c | 300 if (status & 0x240)
|
| /src/sys/arch/arm/nvidia/ |
| tegra210_pinmux.c | 205 TEGRA_PIN("button_home_py1", 0x240, "rsvd0", "rsvd1", "rsvd2", "rsvd3"),
|
| /src/sys/dev/mca/ |
| esp_mca.c | 146 0, 0x240, 0x340, 0x400, 0x420, 0x3240, 0x8240, 0xa240
158 * | \____ I/O base (32B): 001=0x240 010=0x340 011=0x400
|
