HomeSort by: relevance | last modified time | path
    Searched refs:x240 (Results 1 - 25 of 86) sorted by relevancy

1 2 3 4

  /src/external/mit/xorg/etc/etc.hpc/
Makefile.inc 4 etc.hpc/xorg.conf.640x240-jp \
5 etc.hpc/xorg.conf.640x240-us \
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/
nouveau_nvkm_engine_gr_ctxgk20a.c 83 .attrib_nr_max = 0x240,
84 .attrib_nr = 0x240,
  /src/sys/arch/sh3/include/
exception.h 130 #define SH4_INTEVT_IRL0 0x240
137 #define SH4_INTEVT_IRQ2 0x240
  /src/games/bcd/
bcd.c 98 0x404, 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208,
102 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, 0x204,
114 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, 0x204,
118 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, 0x204,
  /src/sys/arch/arm/samsung/
mct_reg.h 45 #define MCT_G_TCON 0x240 /* configuration register */
  /src/sys/arch/x86/pci/
lpssreg.h 76 #define LPSS_REMAP_LO 0x240
  /src/sys/arch/arm/clps711x/
clps711xreg.h 90 #define PS711X_INTSR 0x240 /* Interrupt Status Register (RO) */
  /src/sys/dev/isa/
ioat66.c 67 int ioatbases[NSLAVES]={0x220,0x228,0x240,0x248,0x260,0x268};
essreg.h 166 #define ESS_BASE_VALID(base) ((base) == 0x220 || (base) == 0x230 || (base) == 0x240 || (base) == 0x250)
if_ate.c 81 0x260, 0x280, 0x2A0, 0x240, 0x340, 0x320, 0x380, 0x300
if_fmv_isa.c 79 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x300, 0x340
sbreg.h 58 * either base I/O address 0x220 or 0x240. The encodings below give
291 #define SB_BASE_VALID(base) ((base) == 0x220 || (base) == 0x240 || (base) == 0x260)
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
am4.h 67 #define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240)
  /src/external/lgpl3/gmp/dist/mpn/cray/ieee/
invert_limb.c 67 0x249, 0x247, 0x246, 0x245, 0x243, 0x242, 0x241, 0x240,
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c 421 if (status & 0x240)
425 if (status & 0x240)
amdgpu_vce_v2_0.c 300 if (status & 0x240)
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 334 0x240 MODE_NITRO /* drdu3_vbus_ppc */
  /src/sys/arch/arm/nvidia/
tegra210_pinmux.c 205 TEGRA_PIN("button_home_py1", 0x240, "rsvd0", "rsvd1", "rsvd2", "rsvd3"),
  /src/sys/dev/mca/
esp_mca.c 146 0, 0x240, 0x340, 0x400, 0x420, 0x3240, 0x8240, 0xa240
158 * | \____ I/O base (32B): 001=0x240 010=0x340 011=0x400
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/
imxrt1050-pinfunc.h 124 #define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0
125 #define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0
126 #define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0
127 #define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0
128 #define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0
129 #define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0
imx25-pinfunc.h 50 #define MX25_PAD_A19__A19 0x024 0x240 0x000 0x00 0x000
51 #define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x05 0x000
52 #define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x06 0x000
53 #define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x07 0x000
imx6q-pinfunc.h 695 #define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1
696 #define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0
697 #define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0
698 #define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0
699 #define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0
700 #define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2
701 #define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0
702 #define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0
703 #define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0
imx53-pinfunc.h 783 #define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x240 0x5b8 0x000 0x0 0x0
784 #define MX53_PAD_NANDF_CS2__GPIO6_15 0x240 0x5b8 0x000 0x1 0x0
785 #define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0
786 #define MX53_PAD_NANDF_CS2__ESAI1_TX0 0x240 0x5b8 0x7e4 0x3 0x0
787 #define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 0x240 0x5b8 0x000 0x4 0x0
788 #define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 0x240 0x5b8 0x000 0x5 0x0
789 #define MX53_PAD_NANDF_CS2__MLB_MLBSIG 0x240 0x5b8 0x860 0x6 0x0
790 #define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 0x240 0x5b8 0x000 0x7 0x0
  /src/sys/arch/m68k/060sp/dist/
fplsp.doc 213 0x240: _060LSP__fabss_
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mm-pinfunc.h 616 #define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
617 #define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
618 #define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
619 #define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
620 #define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0

Completed in 50 milliseconds

1 2 3 4