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  /src/sys/arch/evbmips/sbmips/
swarm.h 60 #define DRAM_SMBUS_DEV 0x54
69 #define CFG_DRAM_SMBUS_BASE 0x54 /* starting SMBus device base */
  /src/sys/arch/sbmips/include/
swarm.h 60 #define DRAM_SMBUS_DEV 0x54
69 #define CFG_DRAM_SMBUS_BASE 0x54 /* starting SMBus device base */
  /src/sys/external/bsd/acpica/dist/tools/acpiexec/
aetables.h 164 0x44,0x53,0x44,0x54,0x24,0x00,0x00,0x00, /* 00000000 "DSDT$..." */
167 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
177 0x53,0x53,0x44,0x54,0x3E,0x00,0x00,0x00, /* 00000000 "SSDT>..." */
180 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
181 0x20,0x06,0x12,0x20,0x14,0x19,0x5F,0x54, /* 00000020 " .. .._T" */
183 0x54,0x31,0x20,0x2D,0x20,0x5F,0x54,0x39, /* 00000030 "T1 - _T9" */
189 0x53,0x53,0x44,0x54,0x3E,0x00,0x00,0x00, /* 00000000 "SSDT>..." */
192 0x02,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
193 0x20,0x06,0x12,0x20,0x14,0x19,0x5F,0x54, /* 00000020 " .. .._T" *
    [all...]
  /src/common/lib/libc/arch/sparc/gen/
saveregs.S 59 st %i4, [%fp + 0x54] ! fr->fr_argd[4]
  /src/sys/arch/i386/pci/
via82c586reg.h 32 #define VP3_CFG_PIRQ_REG 0x54 /* PCI configuration space */
amd756reg.h 34 * Edge Triggered Interrupt Select register. (0x54)
53 #define AMD756_CFG_PIR 0x54
  /src/sys/arch/mips/alchemy/dev/
usbdreg.h 61 #define USBD_EP4RDSTAT 0x54 /* EP4 Read FIFO Status */
  /src/sys/arch/pmax/stand/common/
bootinit.S 39 lw v0, 0x54(v0) # offset for callv->_bootinit
  /src/sys/arch/vax/vax/
db_disasm.h 71 ((x) == 0xfffd) ? 0x54 : \
  /src/sys/dev/pci/
pciide_ite_reg.h 37 #define IT_TIM(chan) ((chan) ? 0x58 : 0x54) /* timings */
pciide_ixp_reg.h 35 #define IXP_UDMA_CTL 0x54
pcscpreg.h 53 #define DMA_STAT 0x54 /* Status Register */
nfsmbreg.h 33 #define NFORCE_OLD_SMB2 0x54
  /src/sys/external/bsd/acpica/dist/compiler/
dttemplate.h 160 0x41,0x45,0x53,0x54,0x90,0x03,0x00,0x00, /* 00000000 "AEST...." */
161 0x02,0xE6,0x49,0x4E,0x54,0x45,0x4C,0x20, /* 00000008 "..INTEL " */
162 0x54,0x65,0x6D,0x70,0x6C,0x61,0x74,0x65, /* 00000010 "Template" */
163 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
280 0x54,0x45,0x4D,0x50,0x4C,0x41,0x54,0x45, /* 00000010 "TEMPLATE" */
281 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
288 0x41,0x50,0x4D,0x54,0x94,0x00,0x00,0x00, /* 00000000 "APMT...." */
290 0x54,0x45,0x4D,0x50,0x4C,0x41,0x54,0x45, /* 00000010 "TEMPLATE" *
    [all...]
  /src/sys/external/isc/libsodium/dist/test/default/
scalarmult7.c 6 0x72, 0x20, 0xf0, 0x09, 0x89, 0x30, 0xa7, 0x54, 0x74, 0x8b, 0x7d,
12 0x85, 0x20, 0xf0, 0x09, 0x89, 0x30, 0xa7, 0x54, 0x74, 0x8b, 0x7d,
stream3.c 7 0x46, 0xc7, 0x60, 0x09, 0x54, 0x9e, 0xac,
  /src/sys/arch/arm/cortex/
scu_reg.h 49 #define SCU_NS_ACCESS_CONTROL 0x54 // SCU Non-Secure Access Control
  /src/sys/arch/macppc/macppc/
static_edid.c 44 /* 20 */ 0x1f, 0x50, 0x54, 0x00, 0x08, 0x00, 0x01, 0x01,
67 /* 20 */ 0x25, 0x50, 0x54, 0x01, 0x00, 0x00, 0x01, 0x01,
72 /* 48 */ 0x00, 0x00, 0x00, 0xfe, 0x00, 0x4c, 0x54, 0x31,
75 /* 60 */ 0x54, 0x31, 0x32, 0x31, 0x53, 0x55, 0x2d, 0x31,
  /src/sys/dev/acpi/
fdc_acpireg.h 47 { 15, 2, 30, 2, 0xff, 0xdf, 0x1b, 0x54, 80, 2400, 1, FDC_500KBPS,
  /src/tests/crypto/opencrypto/
h_camellia.c 41 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
46 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10};
  /src/sys/external/bsd/acpica/dist/tools/examples/
extables.c 173 0x52,0x53,0x44,0x20,0x50,0x54,0x52,0x20, /* 00000000 "RSD PTR " */
174 0x43,0x49,0x4E,0x54,0x45,0x4C,0x20,0x02, /* 00000008 "CINTEL ." */
182 0x52,0x53,0x44,0x54,0x28,0x00,0x00,0x00, /* 00000000 "RSDT(..." */
183 0x01,0x10,0x49,0x4E,0x54,0x45,0x4C,0x20, /* 00000008 "..INTEL " */
184 0x54,0x45,0x4D,0x50,0x4C,0x41,0x54,0x45, /* 00000010 "TEMPLATE" */
185 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
191 0x58,0x53,0x44,0x54,0x2C,0x00,0x00,0x00, /* 00000000 "XSDT,..." */
192 0x01,0x06,0x49,0x4E,0x54,0x45,0x4C,0x20, /* 00000008 "..INTEL " */
193 0x54,0x45,0x4D,0x50,0x4C,0x41,0x54,0x45, /* 00000010 "TEMPLATE" *
    [all...]
  /src/sys/dev/microcode/run/
microcode.h 41 0x51, 0x11, 0x42, 0x52, 0x11, 0x42, 0x53, 0x11, 0x42, 0x54, 0x11,
50 0x56, 0x41, 0xd2, 0x02, 0x22, 0x90, 0x70, 0x10, 0xe0, 0x54, 0x7f,
52 0x75, 0x4e, 0x01, 0x75, 0x4f, 0x84, 0x90, 0x70, 0x10, 0xe0, 0x54,
65 0x47, 0xb4, 0x0c, 0x08, 0x90, 0x70, 0x11, 0xe0, 0x54, 0x0f, 0xf5,
89 0xfd, 0x90, 0x05, 0x05, 0xe0, 0x54, 0xfb, 0xf0, 0x44, 0x04, 0xf0,
90 0xed, 0x54, 0xfe, 0x90, 0x05, 0x08, 0xf0, 0xe4, 0xf5, 0x4e, 0xf5,
113 0x60, 0x03, 0x02, 0x14, 0x35, 0x80, 0x1b, 0xe5, 0x48, 0xc4, 0x54,
114 0x0f, 0xf5, 0x43, 0xe5, 0x4a, 0xc4, 0x54, 0x0f, 0xf5, 0x42, 0xe5,
115 0x4c, 0xc4, 0x54, 0x0f, 0xf5, 0x5e, 0xe5, 0x47, 0x64, 0x06, 0x70,
118 0x1b, 0xe5, 0x49, 0xc4, 0x54, 0x0f, 0xf5, 0x43, 0xe5, 0x4b, 0xc4
    [all...]
  /src/sys/arch/alpha/pci/
sioreg.h 47 #define SIO_PCIREG_MAR1 0x54 /* MEMCS# Attribute 1 */
  /src/sys/arch/arm/ep93xx/
epgpioreg.h 102 #define EP93XX_GPIO_FEOI 0x54 /* clear interrupt (W) */
  /src/sys/arch/arm/nvidia/
tegra_timerreg.h 40 #define TMR3_PCR_REG 0x54

Completed in 40 milliseconds

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