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  /src/sys/arch/sparc/include/
cdefs.h 10 #define __ALIGNBYTES ((size_t)0x7)
  /src/common/lib/libc/arch/aarch64/string/
strlen.S 68 ldr x7, [x4], #8 /* load dword */
70 rev x7, x7 /* convert to LE */
75 orr x7, x7, x5 /* prevent NULs */
83 ldr x7, [x4], #8 /* load dword */
85 rev x7, x7 /* convert to LE */
93 sub x6, x7, x11 /* a = X - 1 */
94 orr x7, x7, #MASK8_0x7f /* b = X | 0x7f *
    [all...]
memset.S 142 and x7, x15, x11 /* are already aligned on a block boundary? */
143 cbz x7, .Lblock_aligned
145 sub x7, x10, x7 /* subtract offset from block length */
146 sub x2, x2, x7 /* subtract that from length */
147 asr x7, x7, #4 /* length -> N*16 */
161 cbz x7, .Lblock_aligned /* aligned? just branch */
164 tbz x7, #0, 0f /* fill 16byte? */
167 tbz x7, #1, 1f /* fill 32byte? *
    [all...]
  /src/sys/arch/powerpc/ibm4xx/dev/
rgmiireg.h 38 #define FER_CHCFG_MASK 0x7 /* EMAC n Mask */
42 #define FER_CHCFG_GMII 0x7 /* GMII enabled */
45 #define SSR_SP_MASK 0x7
  /src/sys/arch/mac68k/obio/
ascvar.h 31 #define ASCUNIT(d) ((d) & 0x7)
  /src/sys/arch/pmax/pmax/
pmaxtype.h 47 #define DS_MAXINE 0x7 /* Personal DECstation 5000/xx */
  /src/sys/dev/isa/
tsdioreg.h 38 #define TSDIO_PCDR 0x7
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/sound/
adi,adau1977.h 14 #define ADAU1977_MICBIAS_8V5 0x7
  /src/sys/dev/ic/
pca9564reg.h 48 #define I2CCON_CR_36KHZ (0x7)
49 #define I2CCON_CR_MASK (0x7)
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu7.h 66 #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
68 #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
70 #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
72 #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
74 #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
76 #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
78 #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
80 #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
82 #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
84 #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7.h 66 #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
68 #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
70 #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
72 #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
74 #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
76 #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
78 #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
80 #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
82 #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
84 #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT
    [all...]
ni_reg.h 53 # define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0)
60 # define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4)
80 # define NI_GRPH_REGAMMA_MODE(x) (((x) & 0x7) << 0)
86 # define NI_OVL_REGAMMA_MODE(x) (((x) & 0x7) << 4)
104 # define NI_DP_MSE_SAT_SRC0(x) (((x) & 0x7) << 0)
106 # define NI_DP_MSE_SAT_SRC1(x) (((x) & 0x7) << 16)
119 # define NI_DIG_FE_DIG_MODE(x) (((x) & 0x7) << 16)
125 # define NI_DIG_HPD_SELECT(x) (((x) & 0x7) << 28)
  /src/sys/arch/ia64/stand/common/
bitstring.h 47 (1 << ((bit)&0x7))
81 _name[_startbyte] &= ((0xff >> (8 - (_start&0x7))) | \
82 (0xff << ((_stop&0x7) + 1))); \
84 _name[_startbyte] &= 0xff >> (8 - (_start&0x7)); \
87 _name[_stopbyte] &= 0xff << ((_stop&0x7) + 1); \
98 _name[_startbyte] |= ((0xff << (_start&0x7)) & \
99 (0xff >> (7 - (_stop&0x7)))); \
101 _name[_startbyte] |= 0xff << ((_start)&0x7); \
104 _name[_stopbyte] |= 0xff >> (7 - (_stop&0x7)); \
  /src/lib/libc/arch/aarch64/gen/
_setjmp.S 52 adrp x7, .L_MAGIC
53 ldr x7, [x7, #:lo12:.L_MAGIC]
57 stp x7, x3, [x0, #_JB_MAGIC]
76 adrp x7, .L_MAGIC
77 ldr x7, [x7, #:lo12:.L_MAGIC]
84 cmp x2, x7
  /src/lib/libc/arch/aarch64/sys/
__syscall.S 54 * Finally, load x7 from the stack.
66 mov x6, x7
67 ldr x7, [sp, #0]
  /src/sys/arch/hpcmips/dev/
plumiobusreg.h 47 #define PLUM_IOBUS_IOXCCNT_MASK 0x7
54 #define PLUM_IOBUS_IOXSCNT_MASK 0x7
  /src/sys/dev/pci/
pciide_ixp_reg.h 54 (u) &= ~(0x7 << __ixpshift); \
55 (u) |= (((m) & 0x7) << __ixpshift); \
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/usb/
pd.h 135 ((usbh) << 31 | (usbd) << 30 | ((ufp_cable) & 0x7) << 27 \
136 | (is_modal) << 26 | ((dfp) & 0x7) << 23 | ((conn) & 0x3) << 21 \
211 (((ver) & 0x7) << 29 | ((cap) & 0xf) << 24 | ((conn) & 0x3) << 22 \
212 | ((vcpwr) & 0x7) << 8 | (vcr) << 7 | (vbr) << 6 | ((alt) & 0x7) << 3 \
213 | ((spd) & 0x7))
233 (((ver) & 0x7) << 29 | ((cap) & 0x7) << 24 | ((conn) & 0x3) << 22 \
344 (((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 | ((cbl) & 0x3) << 18
    [all...]
  /src/sbin/newfs_lfs/
config.h 70 #define DFL_LFS_FBMASK 0x7
  /src/sys/arch/sun2/sun2/
control.h 61 #define CONTEXT_MASK 0x7
  /src/sys/dev/i2c/
mpl115areg.h 44 #define MPL115A_B1_LSB 0x7
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/iio/addac/
adi,ad74413r.h 15 #define CH_FUNC_DIGITAL_INPUT_LOGIC 0x7
  /src/sys/arch/hpcmips/vr/
bcureg.h 181 #define BCUROMSPEED_ATIME_10VT (0x7) /* 10VTClock */
208 #define BCUIO0SPEED_RDYRW_10VT (0x7) /* 10VTClock */
226 #define BCUIO0SPEED_RWRDY_6VT (0x7) /* 6VTClock */
244 #define BCUIO0SPEED_CSRW_8VT (0x7) /* 8VTClock */
271 #define BCUIO1SPEED_RDYRW_10VT (0x7) /* 10VTClock */
289 #define BCUIO1SPEED_RWRDY_6VT (0x7) /* 6VTClock */
307 #define BCUIO1SPEED_CSRW_8VT (0x7) /* 8VTClock */
324 #define BCUSPD_WLCDM (0x7<<8) /* access speed 0x0a000000-0affffff */
327 #define BCUSPD_WLCDRFU (0x7<<8) /* LCD RFU */
336 #define BCUSPD_ISAM1T (0x7<<8) /* ISAM 1TClock *
    [all...]
  /src/sys/external/isc/libsodium/dist/src/libsodium/crypto_core/hsalsa20/ref2/
core_hsalsa20_ref2.c 22 uint32_t x0, x1, x2, x3, x4, x5, x6, x7, x8, local
46 x7 = LOAD32_LE(in + 4);
64 x7 ^= ROTL32(x3 + x15, 9);
65 x11 ^= ROTL32(x7 + x3, 13);
66 x15 ^= ROTL32(x11 + x7, 18);
72 x7 ^= ROTL32(x6 + x5, 9);
73 x4 ^= ROTL32(x7 + x6, 13);
74 x5 ^= ROTL32(x4 + x7, 18);
90 STORE32_LE(out + 20, x7);
  /src/sys/dev/sdmmc/
sdmmc_ioreg.h 32 #define SD_ARG_CMD52_FUNC_MASK 0x7
44 #define SD_ARG_CMD53_FUNC_MASK 0x7
59 #define SD_IO_OCR_NUM_FUNCTIONS(ocr) (((ocr) >> 28) & 0x7)
91 #define CCCR_CTL_AS(x) ((x) & 0x7)
113 #define CCCR_FUNC_FS_FN(fn) ((fn) & 0x7)
165 #define SD_IO_SFIC_WLAN 0x7

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