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  /src/sys/arch/ofppc/include/
vmparam.h 12 #define KERNEL2_SR 0xb
  /src/sys/arch/pmax/pmax/
pmaxtype.h 48 #define DS_MIPSFAIR2 0xb /* DECsystem 5500 */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
cros-ec-sbs.dtsi 48 reg = <0xb>;
  /src/lib/libc/gdtoa/
sum.c 44 ULong carry, *xc, *xa, *xb, *xe, y; local in function:sum
58 xb = b->x;
63 y = (*xa & 0xffff) + (*xb & 0xffff) + carry;
65 z = (*xa++ >> 16) + (*xb++ >> 16) + carry;
80 y = *xa++ + *xb++ + carry;
misc.c 288 ULong *x, *xa, *xae, *xb, *xbe, *xc, *xc0; local in function:mult
317 xb = b->x;
318 xbe = xb + wb;
321 for(; xb < xbe; xc0++) {
322 if ( (y = *xb++) !=0) {
339 for(; xb < xbe; xb++, xc0++) {
340 if ( (y = *xb & 0xffff) !=0) {
354 if ( (y = *xb >> 16) !=0) {
371 for(; xb < xbe; xc0++)
532 ULong *xa, *xa0, *xb, *xb0; local in function:cmp
568 ULong *xa, *xae, *xb, *xbe, *xc; local in function:diff
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/thm/
thm_9_0_sh_mask.h 56 #define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb
312 #define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
319 #define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
326 #define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
333 #define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
340 #define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
347 #define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
354 #define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
361 #define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
368 #define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
    [all...]
thm_10_0_sh_mask.h 56 #define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb
168 #define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
175 #define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
182 #define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
189 #define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
196 #define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
203 #define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
210 #define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
217 #define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
224 #define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
    [all...]
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/phy/
phy-qcom-qusb2.h 23 #define QUSB2_V2_HSTX_TRIM_17_4_MA 0xb
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/net/
ti-dp83869.h 33 #define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb
ti-dp83867.h 33 #define DP83867_RGMIIDCTL_3_00_NS 0xb
51 #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
  /src/sys/arch/mips/alchemy/dev/
ausmbus_pscreg.h 227 #define SMBUS_TMR_FAST_PU 0xb
228 #define SMBUS_TMR_FAST_SH 0xb
229 #define SMBUS_TMR_FAST_SU 0xb
231 #define SMBUS_TMR_FAST_CH 0xb
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/pinctrl/
dra.h 26 #define MUX_MODE11 0xb
44 #define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4))
samsung.h 57 #define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb
stm32-pinfunc.h 24 #define AF10 0xb
  /src/sys/arch/bebox/stand/boot/
vreset.c 89 { 0x3d4, 0xb, 0x0e },
134 { 0x3d4, 0xb, 0x0e },
395 { 0xb, 0xb, 0x10 },
396 { 0xc, 0xb, 0x10 },
397 { 0xd, 0xb, 0x10 },
398 { 0xf, 0xb, 0x10 },
399 { 0x10, 0xb, 0x10 },
400 { 0x10, 0xb, 0xf },
401 { 0x10, 0xb, 0xd }
    [all...]
  /src/sys/arch/arm/amlogic/
mesong12a_pinctrl.c 526 GPIO_MUX_PINCTRL_GROUP("spi1_mosi", 0xb, 4, GPIOH_4, 3),
527 GPIO_MUX_PINCTRL_GROUP("spi1_miso", 0xb, 5, GPIOH_5, 3),
528 GPIO_MUX_PINCTRL_GROUP("spi1_ss0", 0xb, 6, GPIOH_6, 3),
529 GPIO_MUX_PINCTRL_GROUP("spi1_clk", 0xb, 7, GPIOH_7, 3),
530 GPIO_MUX_PINCTRL_GROUP("i2c1_sda_h2", 0xb, 2, GPIOH_2, 2),
531 GPIO_MUX_PINCTRL_GROUP("i2c1_sck_h3", 0xb, 3, GPIOH_3, 2),
532 GPIO_MUX_PINCTRL_GROUP("i2c1_sda_h6", 0xb, 6, GPIOH_6, 4),
533 GPIO_MUX_PINCTRL_GROUP("i2c1_sck_h7", 0xb, 7, GPIOH_7, 4),
534 GPIO_MUX_PINCTRL_GROUP("i2c3_sda_h", 0xb, 0, GPIOH_0, 2),
535 GPIO_MUX_PINCTRL_GROUP("i2c3_sck_h", 0xb, 1, GPIOH_1, 2)
    [all...]
  /src/sys/arch/luna68k/dev/
timekeeper.h 67 #define MC_REGB 0xb /* Control register B */
  /src/sys/dev/bluetooth/
bthid.h 47 #define BTHID_DATC 0xb
  /src/sys/external/bsd/drm2/dist/drm/vboxvideo/
vboxvideo_vbe.h 35 #define VBE_DISPI_INDEX_FB_BASE_HI 0xb
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/dma/
x2000-dma.h 19 #define X2000_DMA_UART5_RX 0xb
  /src/sys/arch/hpcmips/vr/
bcureg.h 177 #define BCUROMSPEED_ATIME_14VT (0xb) /* 14VTClock */
204 #define BCUIO0SPEED_RDYRW_14VT (0xb) /* 14VTClock */
222 #define BCUIO0SPEED_RWRDY_10VT (0xb) /* 10VTClock */
240 #define BCUIO0SPEED_CSRW_12VT (0xb) /* 12VTClock */
267 #define BCUIO1SPEED_RDYRW_14VT (0xb) /* 14VTClock */
285 #define BCUIO1SPEED_RWRDY_10VT (0xb) /* 10VTClock */
303 #define BCUIO1SPEED_CSRW_12VT (0xb) /* 12VTClock */
387 #define BCU81SPD_WROMA12T (0xb<<0) /* 12TClock */
  /src/sys/dev/ic/
mc146818reg.h 90 #define MC_REGB 0xb /* Control register B */
135 #define MC_RATE_32_Hz 0xb /* 31.25 ms period */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/
pm8009.dtsi 33 reg = <0xb SPMI_USID>;
  /src/sys/arch/m68k/fpe/
fpu_fmovecr.c 86 } else if (0xb <= offset && offset <= 0xe) {
87 r = &constrom[offset - 0xb + 1];
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
qoriq-fman3-0-1g-3.dtsi 11 cell-index = <0xb>;

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